Table 78. Dcmi Signals; Figure 73. Top-Level Block Diagram - ST STM32F405 Reference Manual

RM0090
15.5.1 DMA interface
The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA
request is generated each time the camera interface receives a complete 32-bit data block
in its register.
15.5.2 DCMI physical interface
The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.
The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the
EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused data pins
must not be assigned to DCMI interface through GPIO alternate functions.
8 bits
10 bits
12 bits
14 bits
PIXCLK
HSYNC
VSYNC
The data are synchronous with PIXCLK and change on the rising/falling edge of the pixel
clock depending on the polarity.
The HSYNC signal indicates the start/end of a line.
The VSYNC signal indicates the start/end of a frame

Figure 73. Top-level block diagram

HCLK
Interrupt DCMI_IT
controller
DMA_REQ

Table 78. DCMI signals

Signal name
D[0..7]
D[0..9]
D[0..11]
D[0..13]
RM0090 Rev 18
Digital camera interface (DCMI)
DCMI_D[0:13]
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DCMI
Signal description
Data
Pixel clock
Horizontal synchronization / Data valid
Vertical synchronization
External
interface
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