Dma Interrupts; Table 37. Dma Interrupt Requests - ST STM32F410 Reference Manual

RM0401
8.4

DMA interrupts

For each DMA stream, an interrupt can be produced on the following events:
•
Half-transfer reached
• Transfer complete
•
Transfer error
• FIFO error (overrun, underrun or FIFO level error)
•
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in
Half-transfer
Transfer complete
Transfer error
FIFO overrun/underrun
Direct mode error
Note: Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.

Table 37. DMA interrupt requests

Interrupt event
RM0401 Rev 3
Direct memory access controller (DMA)
Event flag
HTIF
TCIF
TEIF
FEIF
DMEIF
Table 37.
Enable control bit
HTIE
TCIE
TEIE
FEIE
DMEIE
183/771
197