Execution Cycle Count - Fujitsu F2MC-16LX Hardware Manual

APPENDIX
B.5

Execution Cycle Count

The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
I Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by
adding the number of cycles required for each instruction, "correction value" determined by the
condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction
from memory such as internal ROM connected to a 16-bit bus, the program fetches the
instruction being executed in word increments. Therefore, intervening in data access increases
the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus,
the program fetches every byte of an instruction being executed. Therefore, intervening in data
access increases the execution cycle count. In CPU intermittent operation mode, access to a
general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes
the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low
power consumption mode control register. Therefore, for the cycle count required for instruction
execution in CPU intermittent operation mode, add the "access count x cycle count for the halt"
as a correction value to the normal execution count.
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