Automatic Algorithm Execution Status - Fujitsu MB91260B Series Hardware Manual

32-bit microcontroller
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CHAPTER 17 FLASH MEMORY
17.5

Automatic Algorithm Execution Status

Flash memory is provided with hardware to notify the internal operation status of flash
memory and the completion of the operation to the outside of the flash memory for
executing write/erase operations in the automatic algorithm. One is a ready/busy signal
and the other is a hardware sequence flag.
■ Ready/Busy Signal (RDY/BUSY)
The flash memory has the ready/busy signal in addition to the hardware sequence flag for indicating
whether the internal automatic algorithm is running or completed. This ready/busy signal is connected to
the flash memory interface circuit, and it can be read as the RDY bit of the flash memory status register.
Also, by starting this ready/busy signal, it can generate an interrupt request to the CPU (see "17.1
Overview of Flash Memory").
When the read value of the RDY bit is "0", the flash memory is executing a write or erase operation, where
new write and erase commands are not accepted. When the value of the RDY bit is "1", the flash memory
is in read/write state or in erase operation wait state.
■ Hardware Sequence Flag
Hardware sequence flag can be obtained as data by reading an arbitrary address (or odd number address in
byte access) of the flash memory during automatic algorithm operation. In the data, valid bits are five bits
and each of them indicates the status of the automatic algorithm. Figure 17.5-1 shows the structure of the
hardware sequence flag.
During hardware read
15
During byte read (only for odd address)
During halfword and byte access
7
DPOLL
The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPU programming
mode and read only in halfwords or bytes.
Table 17.5-1 shows a hardware sequence flag status list.
420
Figure 17.5-1 Structure of the Hardware Sequence Flag
(Undefined)
6
5
4
TOGGLE
TLOVER
Undefined
8 7
Hardware sequence flag
7
Hardware sequence flag
3
2
SETIMR
TOGGL2
Undefined
← Bit No.
0
← Bit No.
0
← Bit No.
1
0
Undefined

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