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Fujitsu F2MC-16LX MB90945 Series Hardware Manual

16-bit microcontroller

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FUJITSU SEMICONDUCTOR

CM44-10134-1E

CONTROLLER MANUAL

2

F

MC-16LX

16-BIT MICROCONTROLLER

MB90945 Series

HARDWARE MANUAL

Table of Contents

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Page 1 FUJITSU SEMICONDUCTOR CM44-10134-1E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90945 Series HARDWARE MANUAL...
Page 3 MC-16LX 16-BIT MICROCONTROLLER MB90945 Series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90945 series has been developed as a general-purpose version of the F MC-16LX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC).
Page 6 CHAPTER 10 "I/O PORTS" This chapter explains the functions and operations of the I/O ports. CHAPTER 11 "TIMEBASE TIMER" This chapter explains the functions and operations of the timebase timer. CHAPTER 12 "WATCH-DOG TIMER" This chapter explains the functions and operations of the watch-dog timer. CHAPTER 13 "16-BIT I/O TIMER"...
Page 7 CHAPTER 25 "1M/2M/3M-BIT FLASH MEMORY" This chapter explains the functions and operations of the 1M/2M/3M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer •...
Page 8 FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 Product Overview ..........................2 Features .............................. 3 Block Diagram of MB90V390HA/HB ....................5 Block Diagram of MB90F946A ......................6 Block Diagram of MB90F947(A)/MB90947A ..................7 Block Diagram of MB90F949(A) ......................8 Pin Assignment ........................... 9 Package Dimensions ........................
Page 10 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI OS) ....71 Exceptions ............................74 CHAPTER 4 DELAYED INTERRUPT ................75 Outline of Delayed Interrupt Module ....................76 Delayed Interrupt Register ........................ 77 Delayed Interrupt Operation ......................78 CHAPTER 5 CLOCKS .....................
Page 11 CHAPTER 10 I/O PORTS ....................145 10.1 I/O Ports ............................146 10.2 I/O Port Registers ........................... 147 10.2.1 Port Data Register ........................148 10.2.2 Port Direction Register ......................150 10.2.3 Analog Input Enable Register ....................151 10.2.4 Input Level Select Register (MB90V390HA/HB only) ..............152 CHAPTER 11 TIMEBASE TIMER ...................
Page 12 15.3.2 PPG1 Operation Mode Control Register (PPGC1) ..............222 15.3.3 PPG0/1 Clock Select Register (PPG01) ..................224 15.3.4 Reload Register (PRLL/PRLH) ....................226 15.4 Operations of 8/16-Bit PPG ......................227 15.5 Selecting a Count Clock for 8/16-Bit PPG ..................229 15.6 Controlling Pin Output of 8/16-Bit PPG Pulses ................
Page 13 18.8 Parity Bit ............................294 18.9 Interrupt Generation and Flag Set Timings ..................295 18.9.1 Flag Set Timings for a Receive Operation (Mode 0, mode 1, or mode 3) ......... 296 18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) ............. 297 18.9.3 Flag Set Timings for a Transmit Operation ................
Page 14 20.3 C Interface Operation ........................386 20.4 Programming Flow Charts ......................389 CHAPTER 21 SERIAL I/O ....................391 21.1 Outline of Serial I/O ........................392 21.2 Serial I/O Registers ......................... 393 21.2.1 Serial Mode Control Status Register (SMCS) ................394 21.2.2 Serial Data Register (SDR) .......................
Page 15 22.9 Reception Flowchart of CAN Controller ..................459 22.10 How to Use the CAN Controller ...................... 460 22.11 Procedure for Transmission by Message Buffer (x) ............... 462 22.12 Procedure for Reception by Message Buffer (x) ................464 22.13 Setting Configuration of Multi-level Message Buffer ............... 466 22.14 Setting the CAN Direct Mode Register ...................
Page 16 26.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) ................................532 26.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer) ........................534 APPENDIX ......................... 537 APPENDIX A I/O Maps ..........................538 APPENDIX B Instructions ...........................
Page 17: Chapter 1 Overview
CHAPTER 1 OVERVIEW The MB90945 series is a family member of the F 16LX microcontrollers. 1.1 Product Overview 1.2 Features 1.3 Block Diagram of MB90V390HA/HB 1.4 Block Diagram of MB90F946A 1.5 Block Diagram of MB90F947(A)/MB90947A 1.6 Block Diagram of MB90F949(A) 1.7 Pin Assignment 1.8 Package Dimensions 1.9 Pin Functions...
Page 18: Product Overview
CHAPTER 1 OVERVIEW Product Overview Table 1.1-1 provides an overview of the MB90945 series. ■ Product Overview Table 1.1-1 Product Overview MB90F946A MB90V390HA Features MB90F947(A) MB90947A MB90V390HB MB90F949(A) Product type Evaluation sample Flash version ROM version MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, x6, x8, 1/2 when PLL stop) System clock Minimum instruction execution time: 42 ns (4 MHz osc.
Page 19: Features
CHAPTER 1 OVERVIEW Features Table 1.2-1 lists the features of the MB90945 series. ■ Features Table 1.2-1 MB90945 Features (1 / 2) Features MB90V390HA MB90F946A MB90947A MB90V390HB MB90F947(A) MB90F949(A) UART Full duplex double buffer 1 Channel Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate: 4808/9615/10417/19230/38460/62500/500000bps (asynchronous) 500K/1M/2Mbps (synchronous) at System clock = 20MHz UART (SCI / LIN)
Page 20 CHAPTER 1 OVERVIEW Table 1.2-1 MB90945 Features (2 / 2) Features MB90V390HA MB90F946A MB90947A MB90V390HB MB90F947(A) MB90F949(A) 8/16-bit Supports 8-bit and 16-bit operation modes programmable Twelve 8-bit reload counters pulse generator Twelve 8-bit reload registers for "L" pulse width (6 channels) Twelve 8-bit reload registers for "H"...
Page 21: Block Diagram Of Mb90V390Ha/Hb
CHAPTER 1 OVERVIEW Block Diagram of MB90V390HA/HB Figure 1.3-1 shows a block diagram of the MB90V390HA/HB. ■ Block Diagram of MB90V390HA/HB Figure 1.3-1 Block Diagram of MB90V390HA/HB Clock X0, X1 Controller 16LX with Phase Modulator IO Timer0 FRCK0 30 Kbytes Input Capture IN5 to IN0...
Page 22: Block Diagram Of Mb90F946A
CHAPTER 1 OVERVIEW Block Diagram of MB90F946A Figure 1.4-1 shows a block diagram of the MB90F946A. ■ Block Diagram of MB90F946A Figure 1.4-1 Block Diagram of MB90F946A Clock X0, X1 Controller 16LX with Phase Modulator IO Timer0 FRCK0 Input 16 Kbytes Capture IN5 to IN0 Output...
Page 23: Block Diagram Of Mb90F947(A)/Mb90947A
CHAPTER 1 OVERVIEW Block Diagram of MB90F947(A)/MB90947A Figure 1.5-1 shows a block diagram of the MB90F947(A) and MB90947A. ■ Block Diagram of MB90F947(A)/MB90947A Figure 1.5-1 Block Diagram of MB90F947(A)/MB90947A Clock X0, X1 Controller 16LX with Phase Modulator IO Timer0 FRCK0 6 Kbytes Input Capture...
Page 24: Block Diagram Of Mb90F949(A)
CHAPTER 1 OVERVIEW Block Diagram of MB90F949(A) Figure 1.6-1 shows a block diagram of the MB90F949(A). ■ Block Diagram of MB90F949(A) Figure 1.6-1 Block Diagram of MB90F949(A) Clock X0, X1 Controller 16LX RSTX with Phase Modulator IO Timer0 FRCK0 Input 12 Kbytes Capture IN5 to IN0...
Page 25: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment This chapter shows the pin assignments for the MB90945 series. ■ Pin Assignment of MB90V390HA/HB Figure 1.7-1 Pin Assignment of MB90V390HA/HB (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P04/IN4 P97/FRCK1 P05/IN5...
Page 26 CHAPTER 1 OVERVIEW ■ Pin Assignment of MB90F946A Figure 1.7-2 Pin Assignment of MB90F946A (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P04/IN4 P97/FRCK1 P05/IN5...
Page 27 CHAPTER 1 OVERVIEW ■ Pin Assignment of MB90947A/MB90F947(A)/MB90F949(A) Figure 1.7-3 Pin Assignment of MB90947A/MB90F947(A)/MB90F949(A) (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P04/IN4 P97/FRCK1 P05/IN5...
Page 28: Package Dimensions
3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8 ˚ 0.65(.026) 0.32±0.05 0.17±0.06 0.13(.005) (.013±.002) (.007±.002) 0.25±0.20 0.80±0.20 "A" (.031±.008) (.010±.008) (Stand off) 0.88±0.15 (.035±.006) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2002 FUJITSU LIMITED F100008S-c-5-5...
Page 29: Pin Functions
CHAPTER 1 OVERVIEW Pin Functions Table 1.9-1 describes the pin functions of the MB90945 series. ■ Pin Functions Table 1.9-1 Pin Description (1 / 4) Pin no. Pin name Circuit type Function Oscillation output Oscillation input Reset input 77 to 82 P00 to P05 General-purpose I/O IN0 to IN5...
Page 30 CHAPTER 1 OVERVIEW Table 1.9-1 Pin Description (2 / 4) Pin no. Pin name Circuit type Function General-purpose I/O SCK0 SCK input/output for UART 0 General-purpose I/O SIN0 SIN input for UART 0 General-purpose I/O General-purpose I/O General-purpose I/O ADTG External trigger input of the A/D converter 18, 19 P40, P41...
Page 31 CHAPTER 1 OVERVIEW Table 1.9-1 Pin Description (3 / 4) Pin no. Pin name Circuit type Function 36 to 43 P60 to P67 General-purpose I/O AN0 to AN7 Inputs for the A/D converter 45 to 48 P51 to P54 General-purpose I/O PPG11 to Outputs for the programmable pulse generators PPG14...
Page 32 CHAPTER 1 OVERVIEW Table 1.9-1 Pin Description (4 / 4) Pin no. Pin name Circuit type Function 75, 76 P80, P81 General-purpose I/O For the EVA device, these pins are high current outputs with slewrate control Dedicated power supply pin (5V) for the A/D converter AVRH Dedicated pos.
Page 33: Input-Output Circuits
CHAPTER 1 OVERVIEW 1.10 Input-Output Circuits Table 1.10-1 lists the input-output circuits. ■ Input-output Circuits Table 1.10-1 I/O Circuit Types (1 / 3) Type Circuit Remarks Oscillation feedback resistor: 1 MΩ approx. Clock input P-ch N-ch Standby control signal CMOS hysteresis input with pull-up resistor R(pull-up) CMOS HYS •...
Page 34 CHAPTER 1 OVERVIEW Table 1.10-1 I/O Circuit Types (2 / 3) Type Circuit Remarks • CMOS output (4mA) • Automotive hysteresis input P-ch N-ch Automotive HYS • CMOS output (4mA) • Automotive hysteresis input • Analog input P-ch N-ch P-ch Analog input N-ch Automotive HYS...
Page 35 CHAPTER 1 OVERVIEW Table 1.10-1 I/O Circuit Types (3 / 3) Type Circuit Remarks • CMOS output P21: 4mA P42, P43: 3mA • CMOS hysteresis input P-ch High current N-ch CMOS HYS • EVA/ROM device: CMOS hysteresis input with pull-down resistor •...
Page 36: Handling Device
CHAPTER 1 OVERVIEW 1.11 Handling Device Special care is required for the followings when handling the device: • Preventing latch-up • Treatment of unused pins • Stabilization of power supply voltage • Using external clock • Power supply pins (V •...
Page 37 CHAPTER 1 OVERVIEW ● Using external clock To use external clock, drive the X0 pin and leave X1 pin open. Figure 1.11-1 shows a diagram of how to use external clock. Figure 1.11-1 Using External Clock MB90945 series Open ● Using power supply pins (V Ensure that all V -level power supply pins are the same potential.
Page 38 CHAPTER 1 OVERVIEW ● Pull-up/pull-down resistors The MB90945 series does not support internal pull-up/pull-down resistors. Use external components where needed. ● Crystal oscillator circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
Page 39: Chapter 2 Cpu
CHAPTER 2 This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Memory Space Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-Byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions 2.11 Precautions for Use of "DIV A, Ri"...
Page 40: Outline Of The Cpu
CHAPTER 2 CPU Outline of the CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
Page 41: Memory Space
CHAPTER 2 CPU Memory Space An F MC-16LX CPU has a 16 Mbytes memory space. All data program input and output managed by the F MC-16LX CPU are located in this 16 Mbytes memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■...
Page 42 CHAPTER 2 CPU ■ ROM Area ● Vector table area (address: FFFC00 to FFFFFF This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address.
Page 43 CHAPTER 2 CPU ■ Address Generation Types The F MC-16LX has the following two addressing modes: ● Linear addressing An entire 24-bit address is specified by an instruction. ● Bank addressing The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.
Page 44: Memory Space Map
CHAPTER 2 CPU Memory Space Map The memory space of the MB90945 series is shown in Figure 2.3-1. ■ Memory Space Map The ROM data in the high-order portion of FF bank can be seen as an image in the higher 00 bank in order to support the small model C compiler.
Page 45 CHAPTER 2 CPU Figure 2.3-1 Memory Space Map MB90947A MB90V390HA MB90F947 MB90F949 MB90V390HB MB90F946A MB90F947A MB90F949A FFFFFF FFFFFF FFFFFF FFFFFF ROM (FF bank) ROM (FF bank) ROM (FF bank) ROM (FF bank) FF0000 FF0000 FF0000 FF0000 FEFFFF FEFFFF FEFFFF FEFFFF ROM (FE bank) ROM (FE bank) ROM (FE bank)
Page 46: Linear Addressing
CHAPTER 2 CPU Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32- bit general-purpose register value as the address.
Page 47: Bank Addressing Types
CHAPTER 2 CPU Bank Addressing Types In the bank method, the 16-Mbyte space is divided into 256 64 Kbytes banks. The following five bank registers are used to specify the banks corresponding to each space: • Program counter bank register (PCB) •...
Page 48 CHAPTER 2 CPU Table 2.5-1 Default Space Default space Addressing mode Program space PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 shows an example of a memory space divided into register banks.
Page 49: Multi-Byte Data In Memory Space
CHAPTER 2 CPU Multi-Byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.
Page 50: Registers
CHAPTER 2 CPU Registers The F MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture.
Page 51 CHAPTER 2 CPU ■ General-purpose Registers The F MC-16LX general-purpose registers are located from addresses 000180 to 00037F (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses is currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2.
Page 52: Accumulator (A)
CHAPTER 2 CPU 2.7.1 Accumulator (A) The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data.
Page 53: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution.
Page 54: Processor Status (Ps)
CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
Page 55 CHAPTER 2 CPU ● T: Sticky bit flag: "1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero.
Page 56 CHAPTER 2 CPU ■ Interrupt Level Mask Register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the interrupt level is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1).
Page 57: Program Counter (Pc)
CHAPTER 2 CPU 2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset.
Page 58: Register Bank
CHAPTER 2 CPU Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers.
Page 59 CHAPTER 2 CPU ● Direct page register (DPR) <Initial value: 01 > DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.8-1. DPR is eight bits long, and is initialized to 01 by a reset.
Page 60: Prefix Codes
CHAPTER 2 CPU Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data is determined for each addressing mode.
Page 61 CHAPTER 2 CPU ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180 to 00018F...
Page 62: Interrupt Disable Instructions
CHAPTER 2 CPU 2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC - AND CCR,#imm8 - ADB - CMR - POPW PS - DTB ■...
Page 63: Precautions For Use Of "Div A, Ri" And "Divw A, Rwi" Instructions
CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00 " in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" instructions. ■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.11-1 Precautions for Use of "DIV A, Ri"...
Page 64 CHAPTER 2 CPU Example: If "DIV A,R0" is executed with DTB = "053 " and RP = "03 ", the address of R0 is "0180 " + RP ("03 ") x "10 " + "08 " (R0 corresponding address) = "0001B8 ".
Page 65: Chapter 3 Interrupts
CHAPTER 3 INTERRUPTS This chapter explains the functions and operations of the interrupt. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI 3.9 Exceptions...
Page 66: Outline Of Interrupts
CHAPTER 3 INTERRUPTS Outline of Interrupts The F MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event •...
Page 67 CHAPTER 3 INTERRUPTS ■ Extended Intelligent I/O Service (EI The extended intelligent I/O service automatically transfers data between an internal resource and memory. This processing is traditionally performed by an interrupt processing program, but the EI OS enables data to be transferred in a manner similar to a DMA (direct memory access) operation. To activate the extended intelligent I/O service function from an internal resource, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE).
Page 68: Interrupt Vector
CHAPTER 3 INTERRUPTS Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine.
Page 69 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Vectors (2 / 2) Interrupt control Vector Interrupt Vector Vector Mode register Interrupt cause address request address L address H register bank Number Address INT 23 16-bit Reload Timer 0 FFFFA0 FFFFA1 FFFFA2 Unused 0000B6 ICR06 INT 24...
Page 70: Interrupt Control Registers (Icr)
CHAPTER 3 INTERRUPTS Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following three functions: • Setting an interrupt level for corresponding peripherals •...
Page 71 CHAPTER 3 INTERRUPTS [bit10 to bit8, bit2 to bit0] IL2 to IL0 (interrupt level setting bits) These bits are readable and writable, and specify the interrupt level of the corresponding internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels.
Page 72 CHAPTER 3 INTERRUPTS [bit15 to bit12, bit7 to bit4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits) These bits are write only. These bits specify the EI OS channel. The values set in these bits determine the intelligent I/O service descriptor addresses in memory, which is explained later.
Page 73 CHAPTER 3 INTERRUPTS [bit13, bit12, bit5, bit4] S0, S1 (extended intelligent I/O service status) These bits are read only. The values set in these bits indicate the end condition of EI OS. These bits are initialized to "00 " by a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions.
Page 74: Interrupt Flow
CHAPTER 3 INTERRUPTS Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt Flow Figure 3.4-1 Interrupt Flow I : Flag in CCR ILM : Level register in CPU IF : Internal resource interrupt request IE : Internal resource interrupt enable flag ISE : EI 2 OS enable flag IL : Internal resource interruptrequest level S : Flag in CCR...
Page 75 CHAPTER 3 INTERRUPTS Figure 3.4-2 Register Saving during Interrupt Processing Word (16 bits) "H" SSP (SSP value before interrupt) SSP (SSP value after interrupt) "L"...
Page 76: Hardware Interrupts
CHAPTER 3 INTERRUPTS Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. ■ Hardware Interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: Comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.
Page 77: Hardware Interrupt Operation
CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource with the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU.
Page 78: Occurrence And Release Of Hardware Interrupt
CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program. ■ Occurrence and Release of Hardware Interrupt Figure 3.5-1 Occurrence and Release of Hardware Interrupt Register file Microcode...
Page 79: Multiple Interrupts
CHAPTER 3 INTERRUPTS 3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. For MB90945 series, this includes the address ranges 000000 0000BF , (3100 to 31FF , 3300 to 33FF ), 3500...
Page 80: Software Interrupts
CHAPTER 3 INTERRUPTS Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. A software interrupt occurs whenever the software interrupt instruction is executed.
Page 81 CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and Release of Software Interrupt Register file B unit Microcode Fetch Queue M C - 1 6 LX . C P U Save Instruction bus : Processor status : Interrupt enable flag ILM : Interrupt level mask register : Instruction register B unit: Bus interface unit (1) The software interrupt instruction is executed.
Page 82: Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPTS Extended Intelligent I/O Service (EI The EI OS function automatically transfers data between I/O and memory. An interrupt processing program was conventionally used for such processing, but EI OS enables data transfer to be performed like DMA (direct memory access). ■...
Page 83 CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of Extended Intelligent I/O Service Memory space by IOA Peripheral I/O register I/O register Interrupt request by ICS Interrupt control register Interrupt controller by BAP Buffer (1) I/O requests transfer. (2) The interrupt controller selects the descriptor. (3) The transfer source and destination are read from the descriptor.
Page 84: Extended Intelligent I/O Service Descriptor (Isd)
CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100 and 00017F internal RAM, and consists of the following items: • Data transfer control data • Status data • Buffer address pointer ■...
Page 85 CHAPTER 3 INTERRUPTS ■ I/O Register address Pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. All of high-order addresses (A23 to A16) are "0", and any I/O between addresses 000000 and 00FFFF can be specified.
Page 86: Ei 2 Os Status Register (Iscs)
CHAPTER 3 INTERRUPTS 3.7.2 OS Status Register (ISCS) This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed.
Page 87: Operation Flow Of And Procedure For Using The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPTS Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI Figure 3.8-1 is a diagram of the EI OS operation flow. Figure 3.8-2 is a diagram of the OS use procedure. ■ EI OS Operation Flow Figure 3.8-1 EI OS Operation Flow BAP : Buffer address pointer...
Page 88 CHAPTER 3 INTERRUPTS Figure 3.8-2 EI OS Use Flow Processing by CPU Processing by EI OS initialization Normal (Interrupt request) termination AND (ISE = 1) JOB execution Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI OS execution time for each flow is described below.
Page 89 CHAPTER 3 INTERRUPTS Table 3.8-2 Data Transfer Compensation Values for Extended EI OS Execution Time Internal access I/O address pointer Internal Buffer address pointer access B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.8-3 Interrupt Handling Times Address pointed to by the stack pointer Interpolation value [cycles] External 8-bit...
Page 90: Exceptions
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software.
Page 91: Chapter 4 Delayed Interrupt
CHAPTER 4 DELAYED INTERRUPT This chapter explains the functions and operations of the delayed interrupt. 4.1 Outline of Delayed Interrupt Module 4.2 Delayed Interrupt Register 4.3 Delayed Interrupt Operation...
Page 92: Outline Of Delayed Interrupt Module
CHAPTER 4 DELAYED INTERRUPT Outline of Delayed Interrupt Module The delayed interrupt source module is used to generate interrupts for switching tasks. Using this module, interrupt requests to the F MC-16LX CPU can be issued and canceled by software. ■ Block Diagram of Delayed Interrupt Figure 4.1-1 shows a block diagram of the delayed interrupt source module.
Page 93: Delayed Interrupt Register
CHAPTER 4 DELAYED INTERRUPT Delayed Interrupt Register DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled. ■...
Page 94: Delayed Interrupt Operation
CHAPTER 4 DELAYED INTERRUPT Delayed Interrupt Operation When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. ■...
Page 95: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter describes the clocks used by MB90945 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Registers 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Time 5.6 Connection of an Oscillator or an External Clock to the Microcontroller...
Page 96: Clocks
CHAPTER 5 CLOCKS Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. This internal clock is called the machine clock. One internal clock cycle is called one machine cycle. Other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal PLL oscillation, called a PLL clock.
Page 97 CHAPTER 5 CLOCKS ■ Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls the operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions are affected by switching the main clock and the PLL clock (clock mode) and by a change in the PLL clock multiplier.
Page 98: Block Diagram Of The Clock Generation Block
CHAPTER 5 CLOCKS Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Oscillation stabilization wait time selector ■...
Page 99 CHAPTER 5 CLOCKS ● System clock generation circuit The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator attached to it. Alternatively, an external clock can be input to this circuit. ● PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
Page 100: Clock Selection Registers
CHAPTER 5 CLOCKS Clock Selection Registers This section lists the clock selection registers and describes the function of each register in detail. ■ Clock Selection Registers Figure 5.3-1 shows the clock selection register (CKSCR) and the PLL and special configuration control register (PSCCR).
Page 101: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCKS 5.3.1 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch between the main clock and a PLL clock and is also used to select an oscillation stabilization wait time and a PLL clock multiplier. ■...
Page 102 CHAPTER 5 CLOCKS Table 5.3-1 Clock Selection Register (CKSCR) (1 / 2) Bit name Function bit15 Reserved Note: Always write "1" to this bit. bit14 MCM: This bit indicates whether the main clock or a PLL clock has been selected as the machine Machine clock clock.
Page 103 CHAPTER 5 CLOCKS Table 5.3-1 Clock Selection Register (CKSCR) (2 / 2) Bit name Function bit10 MCS: This bit specifies whether the main clock or a PLL clock is selected as the machine clock. Machine clock • When this bit is "0", a PLL clock is selected. When it is "1", the main clock is selected. selection bit •...
Page 104: Pll And Special Configuration Control Register (Psccr)
CHAPTER 5 CLOCKS 5.3.2 PLL and Special Configuration Control Register (PSCCR) The PLL and Special Configuration Control Register adds the selection of a PLL clock multiplier. ■ Configuration of the PLL and Special Configuration Control Register (PSCCR) Figure 5.3-3 shows the configuration of the PLL and Special Configuration Control Register (PSCCR). Table 5.3-2 describes the function of each bit of the PLL and Special Configuration Control Register (PSCCR).
Page 105 CHAPTER 5 CLOCKS Table 5.3-2 PLL and Special Configuration Control Register (PSCCR) Bit name Function bit15 Reserved bit These bits are reserved bits. • Always write "0" to these bits. bit9 • Reading these bits always returns "X". bit8 CS2: This bit and CS1 and CS0 bits of the Clock selection register (CKSCR) select a PLL clock Additional multiplier multiplier.
Page 106: Clock Mode
CHAPTER 5 CLOCKS Clock Mode Two clock modes are provided: main clock mode and PLL clock mode. ■ Main Clock Mode and PLL Clock Mode ● Main clock mode In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
Page 107 CHAPTER 5 CLOCKS ■ Machine Clock The machine clock may be a PLL clock output from the PLL multiplier circuit or a clock whose frequency is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral functions.
Page 108 CHAPTER 5 CLOCKS Writing "0" to the MCS bit End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 00 End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 01 End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 10 End of PLL clock oscillation stabilization wait &...
Page 109: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCKS Oscillation Stabilization Wait Time When the power is turned on or when stop mode is released, an oscillation stabilization wait time is required after oscillation begins because there is no oscillation. When switching from the main clock to a PLL clock occurs, an oscillation stabilization wait time is also required after PLL oscillation starts.
Page 110: Connection Of An Oscillator Or An External Clock To The Microcontroller
CHAPTER 5 CLOCKS Connection of an Oscillator or an External Clock to the Microcontroller The MB90945 series micro controller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the micro controller. ■...
Page 111 CHAPTER 5 CLOCKS ● Example of connecting an external clock to the microcontroller As shown in the example in Figure 5.6-2, connect an external clock to X0 pin. X1 pin must be open. Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller MB90945 series open...
Page 112 CHAPTER 5 CLOCKS...
Page 113: Chapter 6 Clock Modulator
CHAPTER 6 CLOCK MODULATOR This chapter provides an overview of the clock modulator and its features. It describes the register structure and operations of the clock modulator. CAUTION: Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and MB90V390HA.
Page 114: Overview
CHAPTER 6 CLOCK MODULATOR Overview This section gives an overview of the Clock modulator. ■ Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The modulator mode: phase modulation is supported.
Page 115: Clock Modulator Control Register (Cmcr)
CHAPTER 6 CLOCK MODULATOR Clock Modulator Control Register (CMCR) The control register (CMCR) enables/disables the phase modulation ■ Clock Modulator Control Register (CMCR) Figure 6.2-1 Configuration of the Clock Modulator Control Register (CMCR) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address Initial value...
Page 116 CHAPTER 6 CLOCK MODULATOR ■ Clock Modulator Control Register Contents Table 6.2-1 Function of Each Bit of the Clock Modulator Control Register Bit name Function bit7 PMOD: Writing "0": Phase modulation disabled (initial value). Phase modulation Writing "1": Modulator enabled in phase modulation mode, MCU is running with enable bit phase modulated clock •...
Page 117: Application Note
CHAPTER 6 CLOCK MODULATOR Application Note Startup/stop sequence for phase modulation mode. ■ Recommended Startup Sequence for Phase Modulation Mode start 1. Switch on PLL 2. Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter of the hardware manual).
Page 118 CHAPTER 6 CLOCK MODULATOR...
Page 119: Chapter 7 Resets
CHAPTER 7 RESETS This chapter describes resets for the MB90945 series microcontrollers. 7.1 Resets 7.2 Reset Cause and Oscillation Stabilization Wait Times 7.3 External Reset Pin 7.4 Reset Operation 7.5 Reset Cause Bits 7.6 Status of Pins in a Reset...
Page 120: Resets
CHAPTER 7 RESETS Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector. The four causes of a reset are as follows: •...
Page 121 CHAPTER 7 RESETS ● Software reset A software reset is an internal reset generated by writing "0" to the RST bit of the low-power consumption mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset. ●...
Page 122: Reset Cause And Oscillation Stabilization Wait Times
CHAPTER 7 RESETS Reset Cause and Oscillation Stabilization Wait Times The MB90945 series has four reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset Causes and Oscillation Stabilization Wait Times Table 7.2-1 lists the reset causes and oscillation stabilization wait times. Table 7.2-1 Reset Causes and Oscillation Stabilization Wait Times Oscillation stabilization wait time Reset cause...
Page 123 CHAPTER 7 RESETS Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset EVA: 2 /HCLK /HCLK /HCLK others: 2 /HCLK CPU operation Voltage step-down Oscillation circuit stabilization stabilization wait wait interval time HCLK: Oscillation clock Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several ms, until stabilization at a natural frequency is attained.
Page 124: External Reset Pin
CHAPTER 7 RESETS External Reset Pin The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an "L" level signal generates an internal reset. For the MB90945 series, resets are generated in synchronization with the CPU operating clock. However, the I/O port pins are affected by the external reset pin (RST pin) in an asynchronous manner.
Page 125: Reset Operation
CHAPTER 7 RESETS Reset Operation When a reset is cleared, the memory locations from which the mode data and the reset vectors are read are selected according to the setting of the mode pins, and a mode fetch is performed. Mode setting data determines the CPU operating mode and the execution start address after a reset operation ends.
Page 126 CHAPTER 7 RESETS ■ Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDC "...
Page 127: Reset Cause Bits
CHAPTER 7 RESETS Reset Cause Bits A reset cause can be identified by reading the watch-dog timer control register (WDTC). ■ Reset Cause Bits As shown in Figure 7.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watch-dog timer control register (WDTC).
Page 128 CHAPTER 7 RESETS ■ Correspondence between Reset Cause Bits and Reset Causes Figure 7.5-2 shows the configuration of the reset cause bits of the watch-dog timer control register (WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See "■ Watch-dog timer control register (WDTC)"...
Page 129 CHAPTER 7 RESETS ● Clearing the reset cause bits The reset cause bits are cleared only when the watch-dog timer control register (WDTC) is read. Any bit corresponding to a reset cause that has already been generated is not cleared even though another reset is generated (a setting of "1"...
Page 130: Status Of Pins In A Reset
CHAPTER 7 RESETS Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins during a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). ●...
Page 131: Chapter 8 Low-Power Control Circuit
CHAPTER 8 LOW-POWER CONTROL CIRCUIT This chapter explains the functions and operations of the low-power control circuits. 8.1 Overview of Low Power Consumption Mode 8.2 Block Diagram of the Low-Power Consumption Control Circuit 8.3 Low-Power Consumption Mode Control Register (LPMCR) 8.4 CPU Intermittent Operation Mode 8.5 Standby Mode 8.6 Status Change Diagram...
Page 132: Overview Of Low Power Consumption Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Overview of Low Power Consumption Mode The MB90945 series has the following CPU operating modes, any of which can be used depending on operating clock selection and clock operation control: • Clock mode (PLL clock mode or main clock mode) •...
Page 133 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Clock Mode ● PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. ● Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions.
Page 134 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ● Stop mode The stop mode cause the oscillation to stop. All functions are inactivated. Note: Because the stop mode turn-off the oscillation clock, data can be retained at the lowest power consumption. In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed.
Page 135: Block Diagram Of The Low-Power Consumption Control Circuit
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Block Diagram of the Low-Power Consumption Control Circuit The low-power consumption control circuit consists of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU clock control circuit • Peripheral clock control circuit •...
Page 136 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ● CPU intermittent operation selector This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation mode. ● Standby control circuit The standby control circuit controls the CPU clock control and the peripheral clock control circuits and turns the low-power consumption mode on and off.
Page 137: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also sets the number of CPU clock pulses to halt during the CPU intermittent operation mode. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Page 138 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Table 8.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register (LPMCR) Bit name Function bit7 STP: This bit indicates switching to the stop mode. Stop mode bit • When "1" is written to this bit, a switch to the stop mode is performed. •...
Page 139 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Access to the Low-power Consumption Mode Control Register Writing in the low-power consumption mode control register executes a change in the low-power consumption mode (including the stop mode, sleep mode, and timebase timer mode). Only the instructions listed in Table 8.3-2 should be used for this purpose.
Page 140 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Table 8.3-2 Instructions to be Used for Switching to a Low-power Consumption Mode MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr,A MOV eam,A MOV @RLi+disp8,A MOVP addr24,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi...
Page 141: Cpu Intermittent Operation Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while external buses and peripheral functions continue to operate at high speeds. The purpose of this mode is to reduce power consumption. ■...
Page 142: Standby Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Standby Mode The standby mode includes the sleep (PLL sleep, main sleep), timebase timer, and stop modes. ■ Operation Status during Standby Mode Table 8.5-1 shows operation statuses during standby mode. Table 8.5-1 Operation Status during Standby Mode Condition Main Machine...
Page 143: Sleep Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.1 Sleep Mode This mode stops the CPU operating clock. Other components continue to operate. When the low-power consumption mode control register (LPMCR) indicates a switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode has been set.
Page 144 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Sleep Mode The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt occurs. ● Return by a reset A sleep mode is initialized to the main clock mode by a reset. ●...
Page 145: Timebase Timer Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.2 Timebase Timer Mode This mode causes all functions, excluding oscillation, the timebase timer, and the clock timer, to stop. In this mode, only the timebase timer and clock timer operate. ■ Switching to the Timebase Timer Mode When "0"...
Page 146 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Timebase Timer Mode The low-power consumption control circuit releases the timebase timer mode when a reset is input or an interrupt occurs. ● Return by a reset The timebase timer mode is initialized to the main clock mode by a reset. Note: The RST signal must be asserted for at least 100 µs in Main timebase timer mode.
Page 147: Stop Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.3 Stop Mode Because this mode causes oscillation to stop and inactivates all functions, data can be retained by the lowest power consumption. ■ Switching to the Stop Mode When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR), switching to the stop mode occurs.
Page 148 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Stop Mode The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt occurs. Because oscillation of the operating clock is halted before returning from the stop mode, the low- power consumption control circuit enters the oscillation stabilization wait state, then releases the stop mode.
Page 149 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Notes: • To set a pin to high-impedance when the pin is shared by a peripheral function and a port in stop mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to "1".
Page 150: Status Change Diagram
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Status Change Diagram Figure 8.6-1 shows the status change diagram of the MB90945 series. ■ Status Change Diagram Figure 8.6-1 Status Change Diagram External reset, watch-dog timer reset, software reset Power-on Reset Power-on reset MCS=0 Main clock mode PLL clock mode MCS=1...
Page 151 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Operation Status in Each Operating Mode Table 8.6-1 lists the operation status in each operating mode. Table 8.6-1 Operation Status in Each Operating Mode Main Timebase Clock Operation status PLL clock Peripheral clock timer source Active Active...
Page 152: Usage Notes On Low-Power Consumption Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Usage Notes on Low-Power Consumption Mode Note the following four items when using the low-power consumption mode: • Switching to the standby mode and interrupt • Notes on the transition to standby mode • Release of a standby mode by an interrupt •...
Page 153 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Note: If the CPU does not branch to the interrupt processing routine immediately after a return, action such as interrupt disabling must be taken before a standby mode is set. ■ Release of the Stop Mode The stop mode can be released by an input that has been set as an external interrupt input cause before the system enters the stop mode.
Page 154 CHAPTER 8 LOW-POWER CONTROL CIRCUIT LPMCR, #H’XX ; the low-power mode transition instruction in Table 8.3-2 ; jump to next instruction A, #H’10 ; any instruction The device does not guarantee its operation after returning from the low-power consumption mode if you place an array of instructions other than the one enclosed in the line.
Page 155: Chapter 9 Memory Access Modes
CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 9.1 Outline of Memory Access Modes 9.2 Mode Pins 9.3 Mode Data...
Page 156: Outline Of Memory Access Modes
CHAPTER 9 MEMORY ACCESS MODES Outline of Memory Access Modes In the F MC-16LX, the following two memory access modes are provided for each of the access methods and access areas: • Operation mode • Bus mode ■ Memory Access Modes Operation mode Bus mode Single chip...
Page 157: Mode Pins
CHAPTER 9 MEMORY ACCESS MODES Mode Pins Table 9.2-1 describes the operations specified by combinations of the MD2 to MD0 external pins. ■ Mode Pins Table 9.2-1 Mode Pins and Modes Mode pin setting Reset vector External data Mode name Remarks access area bus width...
Page 158: Mode Data
CHAPTER 9 MEMORY ACCESS MODES Mode Data Mode data is stored at FFFFDF of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence.
Page 159 CHAPTER 9 MEMORY ACCESS MODES Figure 9.3-2 shows the diagram of the correspondence between the access areas and physical addresses for each bus mode. Figure 9.3-2 Access Areas and Physical Addresses in Each Bus Mode FFFFFF ROM (FF bank) FF0000 FEFFFF ROM (FE bank) FE0000...
Page 160 CHAPTER 9 MEMORY ACCESS MODES ■ Recommended Setting Table 9.3-2 lists a sample recommended setting of mode pins and mode data. Table 9.3-2 Sample Recommended Setting of Mode Pins and Mode Data Sample setting Single chip Note: For the MB90945 series devices with Flash memory, the mode data have predetermined values by the hard-wired logic.
Page 161: Chapter 10 I/O Ports
CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. 10.1 I/O Ports 10.2 I/O Port Registers...
Page 162: I/O Ports
CHAPTER 10 I/O PORTS 10.1 I/O Ports Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read.
Page 163: I/O Port Registers
CHAPTER 10 I/O PORTS 10.2 I/O Port Registers There are four types of I/O port registers: • Port data register (PDR0 to PDRB) • Port direction register (DDR0 to DDRB) • Analog input enable register (ADER) • Input level select register (ILSR) ■...
Page 164: Port Data Register
CHAPTER 10 I/O PORTS 10.2.1 Port Data Register Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. •...
Page 165 CHAPTER 10 I/O PORTS ■ Reading the Port Data Register When a port data register is read, the value depends on the corresponding bit in the port direction register and on the current status of the resource that is connected to the same pin (if applicable). The following cases are possible: DDR value Resource...
Page 166: Port Direction Register
CHAPTER 10 I/O PORTS 10.2.2 Port Direction Register When a pin is used as a port, the corresponding pin is controlled as described below: 0: Input mode 1: Output mode ■ Port Direction Register Figure 10.2-3 shows the port direction registers. Figure 10.2-3 Port Direction Registers DDR0 Initial value...
Page 167: Analog Input Enable Register
CHAPTER 10 I/O PORTS 10.2.3 Analog Input Enable Register This register controls the port 6 and port B pins as described below: 0: Port input/output mode 1: Analog input mode If an external pin is used as an analog input for the A/D converter, the corresponding bit should be set to "1".
Page 168: Input Level Select Register (Mb90V390Ha/Hb Only)
CHAPTER 10 I/O PORTS 10.2.4 Input Level Select Register (MB90V390HA/HB only) In MB90V390HA/HB, the input level select register (ILSR) allows to switch from automotive hysteresis input levels to CMOS hysteresis input levels. In the other MB90945 series devices, the input levels are hardwired, and the ILSR register does not exist.
Page 169 CHAPTER 10 I/O PORTS [bit11 to bit0] ILB to IL0 These bits set the input level of the corresponding port. IL0 sets the input level of Port0, ILB sets the input level of PortB. Setting these bits to "0" selects the "Automotive Hysteresis" input level, setting these bits to "1"...
Page 170 CHAPTER 10 I/O PORTS...
Page 171: Chapter 11 Timebase Timer
CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 11.1 Outline of Timebase Timer 11.2 Timebase Timer Control Register 11.3 Operations of Timebase Timer...
Page 172: Outline Of Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.1 Outline of Timebase Timer The timebase timer consists of an 18-bit timebase counter and a control register. The 18-bit timebase counter divides the system clock. The timebase timer issues interrupts at specified intervals based on carry signals of the timebase counter. ■...
Page 173: Timebase Timer Control Register
CHAPTER 11 TIMEBASE TIMER 11.2 Timebase Timer Control Register The timebase timer control register controls interrupts of the timebase timer and can clear the timebase counter. ■ Timebase Timer Control Register (TBTC) Figure 11.2-1 Configuration of the Timebase Timer Control Register (TBTC) Initial value bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 174 CHAPTER 11 TIMEBASE TIMER Table 11.2-1 Function Description of Each Bit of the Timebase Timer Control Register Bit name Function bit15 Reserved This is a reserved bit. When writing data to the TBTC register ensure that "1" is written to this bit. bit14, bit13 Undefined bit12...
Page 175: Operations Of Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.3 Operations of Timebase Timer The timebase timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to stabilize, and interval timer for generating interrupts at specified intervals. ■ Timebase Counter The timebase counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two.
Page 176 CHAPTER 11 TIMEBASE TIMER...
Page 177: Chapter 12 Watch-Dog Timer
CHAPTER 12 WATCH-DOG TIMER This chapter explains the functions and operations of the watch-dog timer. 12.1 Outline of Watch-Dog Timer 12.2 Watch-Dog Timer Operation...
Page 178: Outline Of Watch-Dog Timer
CHAPTER 12 WATCH-DOG TIMER 12.1 Outline of Watch-Dog Timer The watch-dog timer consists of a two-bit watch-dog counter, control register, and watch-dog reset controller. The two-bit watch-dog counter uses the carry signals of an 18-bit timebase counter as a clock source. ■...
Page 179 CHAPTER 12 WATCH-DOG TIMER ■ Watch-dog Timer Control Register (WDTC) Figure 12.1-2 Configuration of Watch-dog Timer Control Register (WDTC) Initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 XXXXX111 Address : PONR WRST ERST SRST 0000A8 R : Read only W : Write only X : Undefined value - : Undefined...
Page 180 CHAPTER 12 WATCH-DOG TIMER [bit1, bit0] WT1, WT0 These bits are used to select the watch-dog timer interval. Only the data items written during watch-dog timer activation are valid. Data items that are written outside watch-dog timer activation are ignored. Table 12.1-2 lists the interval settings.
Page 181: Watch-Dog Timer Operation
CHAPTER 12 WATCH-DOG TIMER 12.2 Watch-Dog Timer Operation The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. ■...
Page 182 CHAPTER 12 WATCH-DOG TIMER Activation The watch-dog timer is activated by writing "0" to the WTE bit of the WDTC register while the watch-dog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watch-dog timer reset interval.
Page 183 CHAPTER 12 WATCH-DOG TIMER ■ Watch-dog timer behavior at reset When any kind of reset is asserted, the watch-dog timer is deactivated and remains inactive after reset is released (Table 12.2-1). Table 12.2-1 : Watch-dog timer clear and stop conditions Mode Reset WDTC...
Page 184 CHAPTER 12 WATCH-DOG TIMER...
Page 185: Chapter 13 16-Bit I/O Timer
CHAPTER 13 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. 13.1 Outline of 16-Bit I/O Timer 13.2 16-Bit I/O Timer Registers 13.3 16-Bit Free Run Timer 13.4 Output Compare 13.5 Input Capture...
Page 186: Outline Of 16-Bit I/O Timer
CHAPTER 13 16-BIT I/O TIMER 13.1 Outline of 16-Bit I/O Timer The MB90945 series contains two 16-bit free run timer modules, two output compare modules, and three input capture modules and supports six input channels and four output channels. The following sections describe the 16-bit free run timer, Output Compare and Input Capture.
Page 187 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture (2 Channels Per One Module) The three input capture modules consist of two 16-bit capture registers and control registers each corresponding to two independent external input pins. Input capture 0 (channels IN0 and IN1) is assigned to free run timer 0 and input capture 1 and 2 (channels IN2, IN3, IN4 and IN5) are assigned to free run timer 1.
Page 188: 16-Bit I/O Timer Registers
CHAPTER 13 16-BIT I/O TIMER 13.2 16-Bit I/O Timer Registers The 16-bit I/O timer has the following three registers: • 16-bit free run timer register • 16-bit output compare register • 16-bit input capture register ■ 16-bit Free Run Timer 0 and 1 bit15 bit0 00352C...
Page 189 CHAPTER 13 16-BIT I/O TIMER ■ 16-bit Input Capture bit15 bit0 003520 H IPCP0/1 Capture register 0/1 003522 H 003524 H Capture register 2/3 IPCP2/3 003526 H 003528 H IPCP4/5 Capture register 4/5 00352A H 000054 H ICS0/1 Control register 0/1 000055 H Control register 2/3 ICS2/3...
Page 190: 16-Bit Free Run Timer
CHAPTER 13 16-BIT I/O TIMER 13.3 16-Bit Free Run Timer The 16-bit free run timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base timer for the output compares and input captures.
Page 191: Data Register
CHAPTER 13 16-BIT I/O TIMER 13.3.1 Data Register The data register can read the count value of the 16-bit free run timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register.
Page 192: Control Status Register
CHAPTER 13 16-BIT I/O TIMER 13.3.2 Control Status Register The control status register sets the operation mode of the 16-bit free run timer, starts and stops the 16-bit free run timer, and controls interrupts. ■ Control Status Register of Free Run Timer (Lower) Figure 13.3-3 Configuration of the Control Status Register of Free Run Timer (TCCSL0/1) Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...
Page 193 CHAPTER 13 16-BIT I/O TIMER Table 13.3-1 Control Status Register of Free Run Timer (Lower) Bit name Function bit7 IVF: This bit is the interrupt request flag bit and clear bit Interrupt request flag • Writing "0": A possible interrupt is cleared. •...
Page 194 CHAPTER 13 16-BIT I/O TIMER ■ Control Status Register of Free Run Timer (Upper) Figure 13.3-4 Configuration of the Control Status Register of Free Run Timer (TCCSH0/TCCSH1) Address: TCCSH0/1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 00352F ECKE 0XXXXXXX 00353F...
Page 195: 16-Bit Free Run Timer Operation
CHAPTER 13 16-BIT I/O TIMER 13.3.3 16-Bit Free Run Timer Operation The 16-bit free run timer starts counting from counter value "0000" after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations.
Page 196 CHAPTER 13 16-BIT I/O TIMER ■ Clearing the Counter upon a Match with Output Compare Register 0 (4) Figure 13.3-6 Clearing the Counter upon a Match with Output Compare Register 0 (4) Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset...
Page 197: Output Compare
CHAPTER 13 16-BIT I/O TIMER 13.4 Output Compare The output compare module consists of two 16-bit compare registers, two compare output pins, and one control register. If the value written to the compare register of this module matches the 16-bit free run timer value, the output level of the pin can be reversed and an interrupt can be issued.
Page 198: Output Compare Register
CHAPTER 13 16-BIT I/O TIMER 13.4.1 Output Compare Register These 16-bit compare registers are compared with the 16-bit free run timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free run timer, a compare signal is generated and the output compare interrupt flag is set.
Page 199: Control Status Register Of Output Compare
CHAPTER 13 16-BIT I/O TIMER 13.4.2 Control Status Register of Output Compare The control status register sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins. ■ Control Status Register of Output Compare (Lower) Figure 13.4-3 Configuration of the Control Status Register of Output Compare (OCS0/OCS2) Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...
Page 200 CHAPTER 13 16-BIT I/O TIMER Table 13.4-1 Control Status Register of Output Compare (Lower) Bit name Function bit7 ICPm: These bits are used as output compare interrupt flags. "1" is set to these bits when the Compare match compare register value matches the 16-bit free-run timer value. While the interrupt enable bit for unit m request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when the ICPm and ICPn bits are set.
Page 201 CHAPTER 13 16-BIT I/O TIMER Control Status Register of Output Compare (Upper) Figure 13.4-4 Configuration of the Control Status Register of Output Compare (OCS1/OCS3) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 000059 0 X X 0 0 0 0 0 OTEm OTEn OTDm OTDn CMOD1 CMOD0...
Page 202 CHAPTER 13 16-BIT I/O TIMER Table 13.4-2 Control Status Register of Output Compare (Upper) (2 / 2) Bit name Function bit9 OTDm: These bits are used to change the pin output level when the compare pin output is Output pin level enabled.
Page 203: 16-Bit Output Compare Operation
CHAPTER 13 16-BIT I/O TIMER 13.4.3 16-Bit Output Compare Operation In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. The CMOD0 and CMOD1 bits can be used to define the corresponding compare registers for each pin.
Page 204 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform with Two Compare Registers when CMOD0 and CMOD1 = "01 " When CMOD0 and CMOD1 = "01 ", the output level of the pin corresponding to compare register 0 (2) is reversed on every match with the register value.
Page 205 CHAPTER 13 16-BIT I/O TIMER Figure 13.4-8 Sample of a Output Waveform when CMOD0 and CMOD1 = "01 " (with Timer Reset by Match) Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset OCCP0 value BFFF OCCP1 value 7FFF OUT0 OUT1 Note: In this figure, the initial value is "0"...
Page 206 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform when CMOD0 and CMOD1 = "10 " The operation mode defined by CMOD0 and CMOD1 = "10 " is intended for the use of three pulse width modulated signals instead of two. If this mode is set to OCU module 1, a match of the timer value with compare register 0 reverses both OUT2 and OUT3.
Page 207 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform when CMOD0 and CMOD1 = "11 " When CMOD0 and CMOD1 = "11 ", the output level of the OUT3 pin is reversed by the compare registers 0, 2 or 3. For the pin OUT1, this setting is identical to CMOD0 and CMOD1 = "01 "...
Page 208 CHAPTER 13 16-BIT I/O TIMER ■ Output Compare Timing In output compare operation, a compare match signal is generated when the free run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter timing.
Page 209: Input Capture
CHAPTER 13 16-BIT I/O TIMER 13.5 Input Capture Input capture detects a rising or falling edge or both edges of an external input signal and stores a 16-bit free run timer value at that time in a register. In addition, input capture can generate an interrupt upon detection of an edge.
Page 210: Input Capture Register Details
CHAPTER 13 16-BIT I/O TIMER 13.5.1 Input Capture Register Details Input capture has the three registers listed. These registers store a value from the 16-bit free running timer when a valid edge of the corresponding external pin input waveform is detected. (The registers must be accessed in word mode. No values can be written to the registers.) •...
Page 211 CHAPTER 13 16-BIT I/O TIMER ■ Control Status Register Figure 13.5-3 Configuration of the Control Status Register (ICS01, ICS23, ICS45) Address: bit15/7 bit14/6 bit13/5 bit12/4 bit11/3 bit10/2 bit9/1 bit8/0 Initial value ICS01: ICPm ICPn ICEm ICEn EGm1 EGm0 EGn1 EGn0 000054 00000000 ICS23:...
Page 212 CHAPTER 13 16-BIT I/O TIMER Table 13.5-2 Input Capture Control Status Register Bits (Upper and Lower) Bit name Function bit15/bit7 ICPn+1/3: This bit is used as interrupt request flag for input capture n and m. Interrupt request flag • "1" is set to this bit upon detection of a valid edge of an external input pin. bit (Input capture •...
Page 213 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Edge Register Figure 13.5-4 Configuration of the Input Capture Edge Register (ICE01, ICE23, ICE45) Initial value Address: bit15/7 bit14/6 bit13/5 bit12/4 bit11/3 bit10/2 bit9/1 bit8/0 X X X X X 0 X X 0035C9 IUCE IEIm IEIn * ICE01 and ICE45 ("X"...
Page 214 CHAPTER 13 16-BIT I/O TIMER Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower) Bit name Function bit15 to bit11/ Undefined bit7 to bit3 bit10 IUCE1/5: This bit selects the capture source for input capture unit 1 and 5, and Input Capture to UART3 is used by UART3-LIN-Operation.
Page 215: 16-Bit Input Capture Operation
CHAPTER 13 16-BIT I/O TIMER 13.5.2 16-Bit Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture register. ■...
Page 216 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Input Timing ● Capture timing for input signals Figure 13.5-6 Capture Timing for Input Signals φ Counter value Input capture input Valid edge Capture signal Capture register Interrupt...
Page 217: Chapter 14 16-Bit Reload Timer (With Event Count Function)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operations of the 16-bit reload timer (with the event count function). 14.1 Outline of 16-Bit Reload Timer (with Event Count Function) 14.2 16-Bit Reload Timer (with Event Count Function) 14.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer 14.4 Underflow Operation of 16-Bit Reload Timer...
Page 218: Outline Of 16-Bit Reload Timer (With Event Count Function)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.1 Outline of 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN0) and one output pin (TOT0), and a control register. The input clock can be selected from one external clock and three types of internal clock.
Page 219: 16-Bit Reload Timer (With Event Count Function)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer has the following two types of registers: • Timer control register (TMCSR0) • 16-bit timer register (TMR0)/16-bit reload register (TMRLR0) ■...
Page 220: Timer Control Status Register (Tmcsr0)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2.1 Timer Control Status Register (TMCSR0) Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = "0". ■ Timer Control Status Register (TMCSR0) Figure 14.2-2 Configuration of the Timer Control Status Register (TMCSR0) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 221 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [bit9 to bit7] MOD2 to MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds.
Page 222 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [bit6] OUTE Output enable bit. The TOT0 pin functions as a general-purpose port when this bit is "0" and as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT0 outputs a square waveform that indicates that counting is in progress.
Page 223: Register Layout Of 16-Bit Timer Register (Tmr0)/16-Bit Reload Register (Tmrlr0)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2.2 Register Layout of 16-Bit Timer Register (TMR0)/ 16-Bit Reload Register (TMRLR0) • TMR0 contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined.
Page 224: Internal Clock And External Clock Operations Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer The machine clock divided by 2 , or 2 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting.
Page 225 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode) The TIN0 pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source.
Page 226: Underflow Operation Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.4 Underflow Operation of 16-Bit Reload Timer An underflow is defined for this timer as the time when the counter value changes from 0000 to FFFF . Therefore, an underflow occurs after (reload register setting + 1) counts.
Page 227: Output Pin Functions Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.5 Output Pin Functions of 16-Bit Reload Timer In reload mode, the TOT0 pin performs toggle output (inverts at each underflow). In one- shot mode, the TOT0 pin functions as a pulse output that shows a particular level while the count is in progress.
Page 228: Counter Operation State
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.6 Counter Operation State The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1" and WAIT = "1"...
Page 229: Chapter 15 8/16-Bit Ppg
CHAPTER 15 8/16-BIT PPG This chapter explains the 8/16-bit PPG and its functions. 15.1 Outline of 8/16-Bit PPG 15.2 Block Diagram of 8/16-Bit PPG 15.3 8/16-Bit PPG Registers 15.4 Operations of 8/16-Bit PPG 15.5 Selecting a Count Clock for 8/16-Bit PPG 15.6 Controlling Pin Output of 8/16-Bit PPG Pulses 15.7 8/16-Bit PPG Interrupts 15.8 Initial Values of 8/16-Bit PPG Hardware...
Page 230: Outline Of 8/16-Bit Ppg
CHAPTER 15 8/16-BIT PPG 15.1 Outline of 8/16-Bit PPG The 8/16-bit programmable pulse generator (PPG) consists of two 8-bit down counters, four 8-bit reload registers, one 16-bit control register, 2 external pulse output signals, and 2 interrupt outputs. The following functions are implemented: ■...
Page 231: Block Diagram Of 8/16-Bit Ppg
CHAPTER 15 8/16-BIT PPG 15.2 Block Diagram of 8/16-Bit PPG Figure 15.2-1 shows the block diagram of the 8/16-bit PPG (ch0). Figure 15.2-2 shows the block diagram of the 8/16-bit PPG (ch1). ■ Block Diagram of 8/16-bit PPG Figure 15.2-1 8-bit PPG ch0 Block Diagram PPG00 output enable PPG00 Peripheral clock 16-division...
Page 232 CHAPTER 15 8/16-BIT PPG Figure 15.2-2 8-bit PPG ch1 Block Diagram PPG10 output enable PPG10 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock PPG10 Output latch Invert Clear Count clock selection PEN1 In MB90945 series, this IRQ signal merged with the channel1 IRQ signal by or loqic.
Page 233 CHAPTER 15 8/16-BIT PPG ● Details of pins in block diagram Table 15.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 15.2-1 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG0 P56/PPG00...
Page 234 CHAPTER 15 8/16-BIT PPG ● Reload register L/H selector This selector detects the current pin output level to select which register value, Low reload register (PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter. ● Count clock selector This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided clocks of the machine clock or the frequency-divided clocks of the timebase timer.
Page 235: 8/16-Bit Ppg Registers
CHAPTER 15 8/16-BIT PPG 15.3 8/16-Bit PPG Registers The 8/16-bit PPG has the following five types of registers: • PPG0 (2, 4, 6, 8, A) Operation Mode Control Register (PPGCn) • PPG1 (3, 5, 7, 9, B) Operation Mode Control Register (PPGCm) •...
Page 236: Ppg0 Operation Mode Control Register (Ppgc0)
CHAPTER 15 8/16-BIT PPG 15.3.1 PPG0 Operation Mode Control Register (PPGC0) PPGC0 is a 8-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG0 Operation Mode Control Register (PPGC0) Figure 15.3-2 Configuration of the PPG0 Operation Mode Control Register (PPGC0) bit7 bit6...
Page 237 CHAPTER 15 8/16-BIT PPG Table 15.3-1 Bit Function Description of the PPG0 Operation Mode Control Register Bit name Function bit7 PEN0: When set to "1", this bit enables the counter operation of the PPG. When operation is Operation enable bit disabled but output is enabled (bit5), a low level is maintained at the output.
Page 238: Ppg1 Operation Mode Control Register (Ppgc1)
CHAPTER 15 8/16-BIT PPG 15.3.2 PPG1 Operation Mode Control Register (PPGC1) PPGC1 is a 8-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG1 Operation Mode Control Register (PPGC1) Figure 15.3-3 Configuration of the PPG1 Operation Mode Control Register bit15 bit14...
Page 239 CHAPTER 15 8/16-BIT PPG Table 15.3-2 Bit Function Description of the PPG1 Operation Mode Control Register Bit name Function bit15 PEN1: When set to "1", this bit enables the counter operation of the PPG. When operation Operation enable bit is disabled but output is enabled (bit13), a low level is maintained at the output. bit13 PE10: When set to "1", this bit enables the pulse output.
Page 240: Ppg0/1 Clock Select Register (Ppg01)
CHAPTER 15 8/16-BIT PPG 15.3.3 PPG0/1 Clock Select Register (PPG01) PPG01 is an 8-bit control register that controls the counter clock of the 8/16-bit PPG. ■ PPG0/1 Clock Select Register (PPG01) Figure 15.3-4 Configuration of the PPG0/1 Clock Select Register (PPG01) bit7 bit6 bit5...
Page 241 CHAPTER 15 8/16-BIT PPG Table 15.3-3 Bit Function Description of the Clock Select Register (PPG01) Bit name Function bit7 to bit5 PCS2 to PCS0: These bits select the operation clock for the down counter of channel 1 as described Count clock selection below.
Page 242: Reload Register (Prll/Prlh)
CHAPTER 15 8/16-BIT PPG 15.3.4 Reload Register (PRLL/PRLH) The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the PCNT down counters. The PRLL and PRLH registers are readable and writable. ■ Reload Registers (PRLL/PRLH) Figure 15.3-5 Configuration of the Reload Registers Reload register H (PRLHn) Address: ch0 003501 ch1 003503...
Page 243: Operations Of 8/16-Bit Ppg
CHAPTER 15 8/16-BIT PPG 15.4 Operations of 8/16-Bit PPG One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ■...
Page 244 CHAPTER 15 8/16-BIT PPG ■ 8/16-bit PPG Output Operation In this block, the ch0 PPG is activated to start counting when "1" is written to bit7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when "1" is written to bit15 (PEN1) of the PPGC1 register.
Page 245: Selecting A Count Clock For 8/16-Bit Ppg
CHAPTER 15 8/16-BIT PPG 15.5 Selecting a Count Clock for 8/16-Bit PPG The count clock used for the operation is supplied from the peripheral clock or the timebase timer. The count clock can be selected from six choices. ■ Selecting a Count Clock for 8/16-bit PPG Select ch0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG01 register, and ch1 clock at bit7 to bit5 (PCS2 to PCS0) of the PPG01 register.
Page 246: Controlling Pin Output Of 8/16-Bit Ppg Pulses
CHAPTER 15 8/16-BIT PPG 15.6 Controlling Pin Output of 8/16-Bit PPG Pulses The pulses generated by this module can be output from external pins PPG00 and PPG10. Controlling Pin Output of 8/16-bit PPG Pulses To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0: PE00, PPGC1: PE10).
Page 247: 8/16-Bit Ppg Interrupts
CHAPTER 15 8/16-BIT PPG 15.7 8/16-Bit PPG Interrupts For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs. ■ 8/16-bit PPG Interrupts In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter.
Page 248: Initial Values Of 8/16-Bit Ppg Hardware
CHAPTER 15 8/16-BIT PPG 15.8 Initial Values of 8/16-Bit PPG Hardware The hardware components of this block are initialized to the following values when reset: ■ Initial Values of 8/16-bit PPG Hardware ● Registers PPGC0 → 0X000XX1 • PPGC1 → 0X000001 •...
Page 249 CHAPTER 15 8/16-BIT PPG In a mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently. Figure 15.8-2 PRL Write Operation Block Diagram ch0 PRL write data ch1 PRL write data Transferred in synchronization with ch1 write in 16-bit Temporary latch PPG mode ch0 write in a mode other...
Page 250 CHAPTER 15 8/16-BIT PPG...
Page 251: Chapter 16 Dtp/External Interrupts
CHAPTER 16 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of the DTP/external interrupts. 16.1 Outline of DTP/External Interrupts 16.2 DTP/External Interrupt Registers 16.3 Operations of DTP/External Interrupts 16.4 Switching between DTP and External Interrupt Requests 16.5 Notes on Using DTP/External Interrupts...
Page 252: Outline Of Dtp/External Interrupts
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.1 Outline of DTP/External Interrupts The data transfer peripheral (DTP) is located between an external peripheral and the MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external peripheral, transfers the request to the F MC-16LX CPU to activate the intelligent I/O service or interrupt processing.
Page 253: Dtp/External Interrupt Registers
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.2 DTP/External Interrupt Registers The DTP/external interrupts has the following three types of registers: • Interrupt/DTP enable register (ENIR: interrupt request enable register) • Interrupt/DTP flag (EIRR: external interrupt request register) • Request level setting register (ELVR: external level register) ■...
Page 254 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ Request Level Setting Register (ELVR: External Level Register) Initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address : 00000000 000032 Initial value bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address : 00000000 000033 R/W: Readable / writable ELVR defines the request event at the external pin.
Page 255: Operations Of Dtp/External Interrupts
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.3 Operations of DTP/External Interrupts When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and issues an interrupt request to the F MC-16LX CPU if the interrupt from this block has the highest priority.
Page 256 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ DTP Operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000 and 0000FF , in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer.
Page 257: Switching Between Dtp And External Interrupt Requests
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.4 Switching between DTP and External Interrupt Requests To switch between DTP and external interrupt requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR.
Page 258: Notes On Using Dtp/External Interrupts
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.5 Notes on Using DTP/External Interrupts Note carefully the following items when using DTP/external interrupts: • Conditions on the externally connected peripheral when DTP is used • DTP/external interrupt operation procedure • External interrupt request level Notes on Using DTP/external Interrupts Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed.
Page 259 CHAPTER 16 DTP/EXTERNAL INTERRUPTS Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are Enabled "H" level Interrupt cause Interrupt request to the interrupt controller Set inactive when the cause F/F is cleared.
Page 260 CHAPTER 16 DTP/EXTERNAL INTERRUPTS...
Page 261 CHAPTER 17 8/10-BIT A/D CONVERTER This chapter explains the functions and operations of the 8/10-bit A/D converter. 17.1 Outline of the 8/10-Bit A/D Converter 17.2 Configuration of the 8/10-Bit A/D Converter 17.3 8/10-Bit A/D Converter Pins 17.4 8/10-Bit A/D Converter Registers 17.5 8/10-Bit A/D Converter Interrupts 17.6 Operation of the 8/10-Bit A/D Converter 17.7 Notes on the 8/10-Bit A/D Converter...
Page 262: Chapter 17 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.1 Outline of the 8/10-Bit A/D Converter Using the RC-type successive approximation conversion method, the 8/10-bit A/D converter converts an analog input voltage into a 10-bit or 8-bit digital value. An input signal is selected from fifteen channels for analog input pins. The conversion can be activated by software and external trigger.
Page 263 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.1-2 8/10-bit A/D Converter Interrupts and EI Interrupt control register Vector table address Interrupt No. Register name Address Lower Upper Bank #31 (1F ICR10 0000BA FFFF80 FFFF81 FFFF82 Available...
Page 264: Configuration Of The 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 Configuration of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has nine blocks: • A/D control status register (ADCS0, ADCS1) • A/D data register (ADCR0, ADCR1) • Clock selector (Input clock selector for activating A/D conversion) •...
Page 265 CHAPTER 17 8/10-BIT A/D CONVERTER ● A/D control status register (ADCS0, ADCS1) This register selects activation by software or another activation trigger, the conversion mode, and the A/D conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and indicates whether the conversion has halted or is in progress.
Page 266: 8/10-Bit A/D Converter Pins
CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 8/10-Bit A/D Converter Pins This section describes the 8/10-bit A/D converter pins and provides pin block diagrams. ■ 8/10-bit A/D Converter Pins The A/D converter pins are also used as general ports. Table 17.3-1 8/10-bit A/D Converter Pins Function Pin name Pin function...
Page 267 CHAPTER 17 8/10-BIT A/D CONVERTER ■ Block Diagram of the 8/10-bit A/D Converter Pins Figure 17.3-2 Block Diagram of the P60/AN0 to P67/AN7 and PB0/AN8 to PB6/AN14pins ADER Analog input PDR read Output latch PDR write (Port data register) Direction latch DDR write standby control (SBL = 1) DDR read...
Page 268: 8/10-Bit A/D Converter Registers
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4 8/10-Bit A/D Converter Registers This section lists the 8/10-bit A/D converter registers. ■ 8/10-bit A/D Converter Registers Figure 17.4-1 8/10-bit A/D Converter Registers Address : bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000D / 00000C ADER1 ADER0...
Page 269: Analog Input Enable/Adc Select Register
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4.1 Analog Input Enable/ADC Select Register The MB90945 series has 15 analog inputs but only one A/D converter with 8 inputs. Therefore, the special bit ADSEL can be used to select the analog input channels. ■...
Page 270: A/D Control Status Register 1 (Adcs1)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4.2 A/D Control Status Register 1 (ADCS1) A/D control status register 1 (ADCS1) selects activation by software or activation trigger, enables or disables interrupt requests, and indicates interrupt request status and whether conversion is halted or in progress. ■...
Page 271 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-1 Function Description of Each Bit of Control Status Register 1 (ADCS1) Bit name Function bit15 BUSY: This bit indicates the operating status of the A/D converter. Busy bit • If the value read from this bit is "0", A/D conversion has halted. If the read value is "1", A/D conversion is in progress.
Page 272: A/D Control Status Register 0 (Adcs0)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4.3 A/D Control Status Register 0 (ADCS0) A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion channel. ■ A/D Control Status Register 0 (ADCS0) Figure 17.4-5 Configuration of the A/D Control Status Register 0 (ADCS0) bit6 bit5 bit4...
Page 273 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0) Bit name Function bit7, MD1, MD0: These bits select the conversion mode of the A/D conversion function. bit6 A/D conversion • The two-bit value of the MD1 and MD0 bits determines the mode that is selected from mode select bit among four modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode.
Page 274: A/D Data Register (Adcr0, Adcr1)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4.4 A/D Data Register (ADCR0, ADCR1) The A/D data register (ADCR0, ADCR1) holds the result of A/D conversion and selects the resolution of A/D conversion. ■ A/D Data Register (ADCR0, ADCR1) Figure 17.4-6 A/D Data Register (ADCR0, ADCR1) Bit11 Bit10 Bit15 Bit14 Bit13 Bit12 Bit1 Bit0...
Page 275 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-3 Function Description of Each Bit of A/D Data Register 0 (ADCR0) Bit name Function bit15 S10: This bit selects an A/D conversion resolution. A/D conversion • Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a resolution selection resolution of 8 bits.
Page 276: 8/10-Bit A/D Converter Interrupts
CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 8/10-Bit A/D Converter Interrupts The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D conversion is set in the A/D data register. This function supports the extended intelligent I/O service (EI OS).
Page 277: Operation Of The 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.6 Operation of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has three conversion modes: single conversion mode, continuous conversion mode, and stop conversion mode. This section describes operation in each mode. ■ Operation in Single Conversion Mode In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted.
Page 278 CHAPTER 17 8/10-BIT A/D CONVERTER ■ Operation in Stop Conversion Mode In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted with a pause after the conversion of each channel. When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts again with the channel specified by the ANS bits.
Page 279: Conversion Using Ei 2 Os
CHAPTER 17 8/10-BIT A/D CONVERTER 17.6.1 Conversion Using EI The 8/10-bit A/D converter can use EI OS transfer the A/D conversion result to memory. ■ Conversion Using EI Figure 17.6-3 shows the operation flow when EI OS is used. Figure 17.6-3 Sample Operation Flowchart when EI OS is Used Start A/D conversion Sample and hold...
Page 280: A/D Conversion Data Protection Function
CHAPTER 17 8/10-BIT A/D CONVERTER 17.6.2 A/D Conversion Data Protection Function When A/D conversion is performed in the interrupt enabled state, the conversion data protection function operates. ■ A/D Conversion Data Protection Function The A/D converter has just one data register that holds conversion data. When a single A/D conversion is completed, the data in the data register is rewritten.
Page 281 CHAPTER 17 8/10-BIT A/D CONVERTER Figure 17.6-4 Operation Flowchart of the Data Protection Function when EI OS is Used Set EI Start continuous A/D conversion End first conversion Store data in the data register Activate EI End second conversion Has EI Halt A/D ended? Store data in the data...
Page 282: Notes On The 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.7 Notes on the 8/10-Bit A/D Converter Notes on using the 8/10-bit A/D converter. ■ Usage Notes on the 8/10-bit A/D Converter ● Analog input pin The A/D input pins are also used as the I/O pins of ports 6 and B. The corresponding port direction register (DDR6 and DDRB) and the analog input enable register (ADER) determine which pin is used for which purpose.
Page 283: Sample Program 1 For The 8/10-Bit A/D Converter (Single Conversion Mode Using Ei 2 Os)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single Conversion Mode Using EI This section contains a sample program for A/D conversion in single conversion mode using EI ■ Sample Program for Single Conversion Mode Using EI ●...
Page 284 CHAPTER 17 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Intermediate buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status register IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 285 CHAPTER 17 8/10-BIT A/D CONVERTER ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#00H ;Stops A/D conversion. Clears and disables the ;interrupt flag. RETI ;Returns from interrupt. CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12 ED_INT1 0FFDCH ; Sets reset vector. START ;...
Page 286: Sample Program 2 For The 8/10-Bit A/D Converter (Continuous Conversion Mode Using Ei 2 Os)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous Conversion Mode Using EI This section contains a sample program for A/D conversion in continuous conversion mode using EI ■ Sample Program for Continuous Conversion Mode Using EI ●...
Page 287 CHAPTER 17 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Middle buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status register IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 288 CHAPTER 17 8/10-BIT A/D CONVERTER LOOP: A,#00H ;Endless loop A,#01H LOOP ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#80H ;Does not stop A/D conversion. Clears and disables ;the interrupt flag RETI ;Returns from interrupt CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12 ED_INT1 0FFDCH ;Sets reset vector...
Page 289: Sample Program 3 For The 8/10-Bit A/D Converter (Stop Conversion Mode Using Ei Os)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop Conversion Mode Using EI This section contains a sample program for A/D conversion in stop conversion mode using EI ■ Sample Program for Stop Conversion Mode Using EI ●...
Page 290 CHAPTER 17 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Middle buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H ;EI2OS status registerr IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 291 CHAPTER 17 8/10-BIT A/D CONVERTER ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#80H ;Does not stop A/D conversion. Clears and disables ;the interrupt flag RETI ;Returns from interrupt CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12 ED_INT1 0FFDCH ;Sets reset vector START ;Sets single-chip mode...
Page 292 CHAPTER 17 8/10-BIT A/D CONVERTER...
Page 293: Chapter 18 Uart0
CHAPTER 18 UART0 This chapter explains the functions and operations of the UART0. 18.1 Features of UART0 18.2 UART0 Block Diagram 18.3 UART0 Registers 18.4 UART0 Operation 18.5 Baud Rate 18.6 Internal and External Clock 18.7 Transfer Data Format 18.8 Parity Bit 18.9 Interrupt Generation and Flag Set Timings 18.10 UART0 Application Example...
Page 294: Features Of Uart0
CHAPTER 18 UART0 18.1 Features of UART0 The UART0 is a serial I/O port for asynchronous or CLK synchronous communication. The MB90945 series contains two UARTs, UART0 and UART3. For UART3 see "CHAPTER 19 UART2/3". ■ Feature of UART0 UART0 has the following features. •...
Page 295: Uart0 Block Diagram
CHAPTER 18 UART0 18.2 UART0 Block Diagram Figure 18.2-1 shows the block diagram of UART0. ■ UART0 Block Diagram Figure 18.2-1 UART0 Block Diagram CONTROL BUS Receive interrupt (to CPU) Dedicated baud rate clock SCK0 Transmit clock Transmit interrupt 16-bit reload timer 0 (to CPU) Receive clock Clock select...
Page 296: Uart0 Registers
CHAPTER 18 UART0 18.3 UART0 Registers The UART0 has the following four registers: • Serial mode control register • Status register • Input data register/output data register • Rate and data register ■ UART0 Registers Figure 18.3-1 UART0 Registers Serial mode control register (UMC0) bit7 bit6 bit5...
Page 297: Serial Mode Control Register (Umc0)
CHAPTER 18 UART0 18.3.1 Serial Mode Control Register (UMC0) UMC0 specifies the operation mode of UART0. Set the operation mode while operation is halted. However, the RFC bit can be accessed during operation. ■ Serial Mode Control Register (UMC0) Figure 18.3-2 Configuration of the Serial Mode Control Register (UMC0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: Initial value...
Page 298 CHAPTER 18 UART0 ■ Serial Mode Control Register (UMC0) Contents Table 18.3-1 Function of Each Bit of the Serial Control Register Bit name Function bit7 PEN: Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0" Parity enable bit in mode 2.
Page 299: Status Register (Usr0)
CHAPTER 18 UART0 18.3.2 Status Register (USR0) USR0 indicates the current state of the UART0 port. ■ Status Register (USR0) Figure 18.3-3 Configuration of the Status Register (USR0) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 000021 Initial value RDRF ORFE TDRE RIE TIE RBF TBF...
Page 300 CHAPTER 18 UART0 ■ Status Register (USR0) Contents Table 18.3-2 Function of Each Bit of the Status Register Bit name Function bit15 RDRF: This flag indicates the state of the UIDR0 (input data register). The flag is set when the receive data Receiver data register is loaded into UIDR0.
Page 301: Input Data Register (Uidr0) And Output Data Register (Uodr0)
CHAPTER 18 UART0 18.3.3 Input Data Register (UIDR0) and Output Data Register (UODR0) UIDR0 (input data register) is the serial data input register. UODR0 (output data register) is the serial data output register. The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most significant bit (D7) is ignored if the data length is 7 bits.
Page 302: Rate And Data Register (Urd0)
CHAPTER 18 UART0 18.3.4 Rate and Data Register (URD0) URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the most significant bit (bit8) of the data when the transmit data length is 9 bits. Set the baud rate and parity when UART0 is halted.
Page 303 CHAPTER 18 UART0 ■ Rate and Data Register (URD0) Contents Table 18.3-3 Function of Each Bit of the Rate and Data Register Bit name Function bit15, BCH, BCH0: Specifies the machine cycles for the baud rate clock (see Section "18.4 UART0 bit10 Baud rate clock Operation"...
Page 304: Uart0 Operation
CHAPTER 18 UART0 18.4 UART0 Operation Table 18.4-1 lists the operating modes for UART0. Set the UMC0 register to switch between modes. ■ UART0 Operation Modes Table 18.4-1 UART0 Operating Modes Mode Parity Data length Clock mode Length of stop bits CLK asynchronous or CLK 1 bit or 2 bits synchronous...
Page 305: Baud Rate
CHAPTER 18 UART0 18.5 Baud Rate When the dedicated baud rate generator is used, the following two types of baud rates are available: • CLK synchronous baud rate • CLK asynchronous baud rate ■ CLK Synchronous Baud Rate The five URD0 register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous transfer.
Page 306 CHAPTER 18 UART0 Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1, and RC0. The following settings are available. Φ Baud rate = [bps] (machine cycle = 24 MHz) Φ Baud rate = [bps] (machine cycle = 16 MHz) Φ...
Page 307 CHAPTER 18 UART0 Table 18.5-1 Baud Rate CLK asynchronous (µs/Baud) CLK synchronous (µs/Baud) 24 MHz 20 MHz 16 MHz 12 MHz 24 MHz 20 MHz 16 MHz 12 MHz asynchronous divider ratio BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ 0=00 0=11 0=01...
Page 308: Internal And External Clock
CHAPTER 18 UART0 18.6 Internal and External Clock Setting RC3 to RC0 to "1101 " selects the clock signal from the 16-bit reload timer 0. Setting RC3 to RC0 to "1111 " selects the external clock. The external clock frequency has a maximum value of 2 MHz.
Page 309: Transfer Data Format
CHAPTER 18 UART0 18.7 Transfer Data Format UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 shows the relationship between the transmit/receive clock and the data for CLK synchronous mode. ■ Transfer Data Format Figure 18.7-1 Transfer Data Format SCK0 SIN0, SOT0 ⎫...
Page 310: Parity Bit
CHAPTER 18 UART0 18.8 Parity Bit The P bit in the URD0 register specifies whether to use even or odd parity when parity is enabled. The PEN bit in the UMC0 register enables parity. ■ Parity Bit Inputting the data shown in Figure 18.8-1 to SIN0 when even parity is set causes a receive parity error. Figure 18.8-1 also shows the data transmitted when sending 001101 with even parity and odd parity.
Page 311: Interrupt Generation And Flag Set Timings
CHAPTER 18 UART0 18.9 Interrupt Generation and Flag Set Timings UART0 has two interrupt causes and six flags. The two interrupt causes are the receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For reception, the RDRF, ORFE, and PE flags request an interrupt.
Page 312: Flag Set Timings For A Receive Operation (Mode 0, Mode 1, Or Mode 3)
CHAPTER 18 UART0 18.9.1 Flag Set Timings for a Receive Operation (Mode 0, mode 1, or mode 3) The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated when the final stop bit is detected indicating the end of reception transfer. The data in UIDR0 is invalid when either the ORFE or PE bit is active.
Page 313: Flag Set Timings For A Receive Operation (In Mode 2)
CHAPTER 18 UART0 18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) The RDRF flag is set when the final stop bit is detected and reception transfer ends with the last data bit (D8) having the value "1". The ORFE flag is set when the final stop bit is detected, irrespective of the value of the last data bit (D8).
Page 314: Flag Set Timings For A Transmit Operation
CHAPTER 18 UART0 18.9.3 Flag Set Timings for a Transmit Operation TDRE is set and an interrupt request to the CPU is generated when the data written in UODR0 register is transferred to the internal shift register and the next data can be written to UODR0.
Page 315: Status Flag During Transmit And Receive Operation
CHAPTER 18 UART0 18.9.4 Status Flag During Transmit and Receive Operation RBF is set when the start bit is detected and cleared when a stop bit is detected. The receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0 becomes valid at the RDRF set timing.
Page 316: 18.10 Uart0 Application Example
CHAPTER 18 UART0 18.10 UART0 Application Example Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure 18.9-7.) ■ Application Example Figure 18.10-1 RBF Set Timing (Mode 0) SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7 RDRF, PE, ORFE...
Page 317 CHAPTER 18 UART0 Figure 18.10-3 Communication Flowchart for Mode 2 Operation (Host CPU) (Slave CPU) Start Start Set the transfer mode to "3" Set the transfer mode to "2" Receive a byte Set the slave CPU selection in D0 to D7. Set D8 to "1". Transfer the byte.
Page 318 CHAPTER 18 UART0...
Page 319 CHAPTER 19 UART2/3 This chapter explains the functions and operations of the UART2/3. 19.1 Overview of UART2/3 19.2 Configuration of UART2/3 19.3 UART2/3 Pins 19.4 UART2/3 Registers 19.5 UART2/3 Interrupts 19.6 UART2/3 Baud Rates 19.7 Operation of UART2/3 19.8 Notes on Using UART2/3...
Page 320: Chapter 19 Uart2/3
CHAPTER 19 UART2/3 19.1 Overview of UART2/3 The UART2/3 with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. UART2/3 provide bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working both as master or as slave device).
Page 321 CHAPTER 19 UART2/3 Table 19.1-1 UART2/3 Functions (2 / 2) Item Function Master-slave communication One-to-n communication (one master to n slaves) function (This function is supported both for master and slave system) (multiprocessor mode) Synchronous mode Function as Master- or Slave-UART Transceiving pins Direct access possible LIN bus options...
Page 322 CHAPTER 19 UART2/3 ■ UART2/3 Operation Modes The UART2/3 operate in four different modes, which are determined by the MD0- and the MD1-bit of the serial mode register (SMR2/3). Mode 0 and mode 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication.
Page 323 CHAPTER 19 UART2/3 ■ UART2/3 Interrupt and EI Table 19.1-4 UART2/3 Interrupt and EI Interrupt control register Vector table address Interrupt Interrupt cause number Register Address Lower Upper Bank name UART2 #39(27 0000BE FFFF60 FFFF61 FFFF62 reception ICR14 interrupt UART2 #40(28 0000BE FFFF5C...
Page 324: Configuration Of Uart2/3
CHAPTER 19 UART2/3 19.2 Configuration of UART2/3 This section provides a short overview on the building blocks of UART2/3. ■ Block Diagram of UART2/3 UART2/3 consists of the following blocks: • Reload counter • Reception control circuit • Reception shift register •...
Page 325 CHAPTER 19 UART2/3 Figure 19.2-1 Block Diagram of UART2/3 (OTO, ORE FRE EXT, Machine clock REST) transmission clock LBIE Reload Interrupt reception clock Counter Generation TRANSMISSION SCK2/3 circuit CONTROL RECEPTION CIRCUIT CONTROL CIRCUIT Start bit Transmission Detection Start circuit reception circuit Restart Reception Reload Counter...
Page 326 CHAPTER 19 UART2/3 ■ Explanation of the Different Blocks ● Reload counter The reload counter functions as the dedicated baud rate generator. It can select external input clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the reload value.
Page 327 CHAPTER 19 UART2/3 ● Oversampling unit The oversampling unit oversamples the incoming data at the SIN2/3 pin for five times with the machine clock. It is not operated in synchronous operation mode. ● Interrupt generation circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
Page 328 CHAPTER 19 UART2/3 ● Serial control register (SCR2/3) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 •...
Page 329: Uart2/3 Pins
CHAPTER 19 UART2/3 19.3 UART2/3 Pins This section describes the UART2/3 pins and provides a pin block diagram. ■ UART2/3 Pins The UART2/3 pins also serve as general ports. Table 19.3-1 lists the pin functions, I/O formats, and settings required to use UART2/3. Table 19.3-1 UART2/3 Pins Standby Pin name...
Page 330 CHAPTER 19 UART2/3 Figure 19.3-1 Block Diagram of UART2/3 Pins Resource input (*) Resource output Port data register (PDR) Resource output enable PDR read Output latch PDR write Port direction register (DDR) General purpose I/O /SIN2/3 General purpose I/O /SCK2/3 Direction latch General purpose I/O /SOT2/3 DDR write...
Page 331: Uart2/3 Registers
CHAPTER 19 UART2/3 19.4 UART2/3 Registers The following figure shows the UART2/3 registers. ■ UART2/3 Registers Figure 19.4-1 UART2/3 Registers Address : bit 15 bit 8 bit 7 bit 0 003519 , 003518 SCR3 (Serial control register) SMR3 (Serial mode register) 00351B , 00351A SSR3 (Serial status register)
Page 332: Serial Control Register (Scr2/3)
CHAPTER 19 UART2/3 19.4.1 Serial Control Register (SCR2/3) These registers specify parity bits, select the stop bit and data lengths, select a frame data format in mode 1, clear the reception error flag, and specify whether to enable transmission and reception. ■...
Page 333 CHAPTER 19 UART2/3 Table 19.4-1 Functions of Each Bit of Control Register (SCR2/3) Bit name Function bit15 PEN: This bit selects whether to add a parity bit during transmission or detect it during Parity enable bit reception. Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR2/3 is selected. This bit is fixed to "0"...
Page 334: Serial Mode Register (Smr2/3)
CHAPTER 19 UART2/3 19.4.2 Serial Mode Register (SMR2/3) These registers select an operation mode and baud rate clock and specify whether to enable output of serial data and clocks to the corresponding pin. ■ Serial Mode Register (SMR2/3) Figure 19.4-3 Configuration of the Serial Mode Register (SMR2/3) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: Initial value...
Page 335 CHAPTER 19 UART2/3 Table 19.4-2 Bit Function of the Serial Mode Register (SMR2/3) Bit name Function bit7, MD1, MD0: These two bits set the UART2/3 operation mode. bit6 Operation mode selection bits bit5 OTO: This bit sets an external clock directly to the LIN-UART2/3’s serial clock. This function One-to-one external is used for operating mode 2 (synchronous) slave mode operation.
Page 336: Serial Status Register (Ssr2/3)
CHAPTER 19 UART2/3 19.4.3 Serial Status Register (SSR2/3) These registers check the transmission and reception status and error status, and enable and disable the transmission and reception interrupts. ■ Serial Status Register (SSR2/3) Figure 19.4-4 Configuration of the Serial Status Register (SSR2/3) Initial value Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 337 CHAPTER 19 UART2/3 Table 19.4-3 Functions of Each Bit of Status Register (SSR2/3) Bit name Function bit15 This bit is set to "1" when a parity error occurs during reception at PEN=1 and is cleared Parity error flag when "1" is written to the CRE bit of the serial mode register (SCR2/3). •...
Page 338: Reception And Transmission Data Register (Rdr2/3 And Tdr2/3)
CHAPTER 19 UART2/3 19.4.4 Reception and Transmission Data Register (RDR2/3 and TDR2/3) The reception data register (RDR2/3) holds the received data. The transmission data register (TDR2/3) holds the transmission data. Both RDR2/3 and TDR2/3 registers are located at the same address. ■...
Page 339 CHAPTER 19 UART2/3 ■ Transmission Data Register (TDR2/3) When data to be transmitted is written to the transmission data register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOT2/3 pin).
Page 340: Extended Status/Control Register (Escr2/3)
CHAPTER 19 UART2/3 19.4.5 Extended Status/Control Register (ESCR2/3) This register provides several LIN functions, direct access to the SIN2/3 and SOT2/3 pin and setting for UART2/3 synchronous clock mode. ■ Extended Status/Control Register (ESCR2/3) Figure 19.4-6 Configuration of the Extended Status/Control Register (ESCR2/3) Initial value Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 341 CHAPTER 19 UART2/3 Table 19.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/3) Bit name Function bit15 LBIE: This bit enables/disables LIN synch break interrupt LIN synch break LIN synch break interrupt is connected to the reception interrupt. When the LBD bit is detection interrupt set and this bit is "1", a reception interrupt is signaled to the interrupt controller.
Page 342: Extended Communication Control Register (Eccr2/3)
CHAPTER 19 UART2/3 19.4.6 Extended Communication Control Register (ECCR2/3) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN synch break generation. ■ Extended Communication Control Register (ECCR2/3) Figure 19.4-7 Configuration of the Extended Communication Control Register (ECCR2/3) Initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address:...
Page 343 CHAPTER 19 UART2/3 Table 19.4-6 Function of Each Bit of the Extended Communication Control Register (ECCR2/3) Bit name Function bit7 This bit is undefined. Always write "0". bit6 LBR: Writing "1" to this bit generates a LIN synch break of the length selected by the LBL0/1 Generating LIN bits of the ESCR2/3, if operation mode 3 is selected.
Page 344: Baud Rate Generator Register 0/1 (Bgr02/03 And Bgr12/13)
CHAPTER 19 UART2/3 19.4.7 Baud Rate Generator Register 0/1 (BGR02/03 and BGR12/13) The baud rate generator registers 0 and 1 (BGR02/03 and BGR12/13) set the division ratio for the serial clock. Also the actual count of the transmission reload counter can be read.
Page 345: Uart2/3 Interrupts
CHAPTER 19 UART2/3 19.5 UART2/3 Interrupts UART2/3 uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDR2/3), or a reception error occurs.
Page 346 CHAPTER 19 UART2/3 ● Reception interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the serial status register (SSR2/3) is set to "1": • Data reception is complete, i. e. the received data was transferred from the received shift register to the reception data register (RDR2/3): RDRF=1 •...
Page 347 CHAPTER 19 UART2/3 ● LIN synch field edge detection interrupts This paragraph is only relevant, if UART2/3 operates in mode 3 as a LIN slave. After a LIN synch break detection, the next falling edge of the reception bus is indicated by UART2/3. Simultaneously an internal signal connected to the ICU1/ICU3/ICU5 is set to "1".
Page 348 CHAPTER 19 UART2/3 ■ UART2/3 EI OS Functions UART2/3 has a circuit for operating EI OS, which can be started up for either reception or transmission interrupts. ● For UART2 reception UART2 shares the interrupt registers with the UART2 transmission interrupts and with UART3 reception and transmission interrupts.
Page 349: Reception Interrupt Generation And Flag Set Timing
CHAPTER 19 UART2/3 19.5.1 Reception Interrupt Generation and Flag Set Timing The followings are the reception interrupt causes: completion of reception (SSR2/3: RDRF) and occurrence of a reception error (SSR2/3: PE, ORE, or FRE). ■ Reception Interrupt Generation and Flag Set Timing Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) and the reception interrupt enable (RIE) flag bit of the serial status register (SSR2/3) was set to "1".
Page 350: Transmission Interrupt Generation And Flag Set Timing
CHAPTER 19 UART2/3 19.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR2/3) to transmission shift register and started. ■ Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated, when the next data to be sent is ready to be written to the transmission data register (TDR2/3), i.
Page 351 CHAPTER 19 UART2/3 ■ Transmission Interrupt Request Generation Timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR2/3: TIE=1), transmission interrupt request is generated. Note: A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to "1"...
Page 352: Uart2/3 Baud Rates
CHAPTER 19 UART2/3 19.6 UART2/3 Baud Rates One of the followings can be selected for the UART2/3 serial clock source: • Dedicated baud rate generator (Reload Counter) • External clock as it is (clock input to the SCK2/3 pin) • External clock connected to the baud rate generator (Reload Counter) ■...
Page 353 CHAPTER 19 UART2/3 Figure 19.6-1 Baud Rate Selection Circuit (Reload Counter) for UART2/3 REST Start bit falling Reload Value: v edge detected Rxc = 0? Reception Reception Reload clock 15-bit reload counter reset Rxc = v/2? Reload Value: v Machine clock Txc = 0? Transmission 15-bit reload counter...
Page 354: Setting The Baud Rate
CHAPTER 19 UART2/3 19.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate Both 15-bit reload counters are programmed by the baud rate generator registers 0, 1 (BGR02/03 and BGR12/13).
Page 355 CHAPTER 19 UART2/3 ■ Suggested Division Ratios for Different Machine Speeds and Baud Rates The following settings are suggested for different MCU clock speeds and baud rates: Table 19.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds 8 MHz 10 MHz 16 MHz 20 MHz...
Page 356 CHAPTER 19 UART2/3 ■ Using External Clock If the EXT bit of the SMR2/3 is set, an external clock is selected, which has to be connected to the SCK2/3 pin. The external clock is used in the same way as the machine clock to the baud rate reload counter. If One-to-one External Clock Input Mode (SMR2/3: OTO) is selected the SCK2/3 signal is directly connected to the UART2/3 serial clock inputs.
Page 357: 19.6.2 Restarting The Reload Counter
CHAPTER 19 UART2/3 19.6.2 Restarting the Reload Counter The Reload Counters can be restarted of the following reasons: Transmission and reception reload counter: • Global MCU reset • UART2/3 programmable clear (SMR2/3:UPCL bit) • User programmable restart (SMR2/3: REST bit) Reception reload counter: •...
Page 358 CHAPTER 19 UART2/3 ● Clearing reload counters The baud rate reload/counter register (BGR12/13 and BGR02/03) and the baud rate reload counters are cleared to "0" by the MCU global reset and the counters stop. The reload counters are cleared to "0" by writing "1"...
Page 359: Operation Of Uart2/3
CHAPTER 19 UART2/3 19.7 Operation of UART2/3 UART2/3 operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and mode 3 for bidirectional communication as master or slave, and in mode 1 as master or slave multiprocessor communication. ■...
Page 360 CHAPTER 19 UART2/3 ■ Inter-CPU Connection Method External clock one-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: •...
Page 361: Operation In Asynchronous Mode (Operation Mode 0 And Mode 1)
CHAPTER 19 UART2/3 19.7.1 Operation in Asynchronous Mode (Operation Mode 0 and Mode 1) When UART2/3 is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode (Operation Mode 0 and Mode 1) ●...
Page 362 CHAPTER 19 UART2/3 ● Transmission operation If the transmission data register empty (TDRE) flag bit of the serial status register (SSR2/3) is "1", transmission data is allowed to be written to the transmission data register (TDR2/3). When data is written, the TDRE flag goes "0".
Page 363: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 19 UART2/3 19.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for UART2/3 operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the extended communication control register (ECCR2/3) is "0".
Page 364 CHAPTER 19 UART2/3 ● Clock supply In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits for the data including start and stop bits. If the MS bit of the ECCR2/3 register is "0" (master mode) and the SCKE bit of the SMR2/3 register is "1"...
Page 365 CHAPTER 19 UART2/3 ● Communication For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR02/03 and BGR12/13): Set the desired reload value for the dedicated baud rate reload counter Serial mode control register (SMR2/3): MD1, MD0: "10 "...
Page 366: Operation With Lin Function (Operation Mode 3)
CHAPTER 19 UART2/3 19.7.3 Operation with LIN Function (Operation Mode 3) UART2/3 can be used either as LIN Master or LIN Slave. For this LIN function a special mode is provided. Setting the UART2/3 to mode 3 configures the data format to 8N1- LSB-first format.
Page 367 CHAPTER 19 UART2/3 represents 8 times of the baud rate clock cycle. Therefore, baud rate setting value is summarized as follows: without free run timer overflow : BGR value = {(b-a)×Fe/(8×φ)}-1 with free run timer overflow : BGR value = {(max+b-a)×Fe/(8×φ)}-1 where max is the free run timer maximum value at the overflow occurs.
Page 368 CHAPTER 19 UART2/3 Figure 19.7-7 shows a typical start of a LIN message frame and the behavior of the UART2/3. Figure 19.7-7 UART2/3 Behavior as Slave in LIN Mode Serial clock Serial Input (LIN bus) LBR cleared by CPU Internal Synch break (e.
Page 369: Direct Access To Serial Pins
CHAPTER 19 UART2/3 19.7.4 Direct Access to Serial Pins UART2/3 allows the user to directly access to the transmission pin (SOT2/3) or the reception pin (SIN2/3). ■ UART2/3 Direct Pin Access The UART2/3 provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial data by reading the SIOP bit of the ESCR2/3.
Page 370: Bidirectional Communication Function (Normal Mode)
CHAPTER 19 UART2/3 19.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or mode 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 19.7-9 are required to operate UART2/3 in normal mode (operation mode 0 or mode 2).
Page 371 CHAPTER 19 UART2/3 ● Inter-CPU connection As shown in Figure 19.7-10, interconnect two CPUs in UART2/3 mode 2 Figure 19.7-10 Connection Example of UART2/3 Mode 2 Bidirectional Communication Input Output CPU-1 (Master) CPU-2 (Slave) Figure 19.7-11 Example of Bidirectional Communication Flowchart (Transmission side) (Reception side) Start...
Page 372: Master-Slave Communication Function (Multiprocessor Mode)
CHAPTER 19 UART2/3 19.7.6 Master-Slave Communication Function (Multiprocessor Mode) UART2/3 communication with multiple CPUs connected in master-slave mode is available for both master and slave systems. ■ Master-slave Communication Function The settings shown in Figure 19.7-12 are required to operate UART2/3 in multiprocessor mode (operation mode 1).
Page 373 CHAPTER 19 UART2/3 ● Function selection Select the operation mode and data transfer mode for master/slave communication as shown in Table 19.7- Table 19.7-3 Selection of the Master/Slave Communication Function Operation mode Synchronization Stop Data Parity method direction Master CPU Slave CPU Address A/D="1"...
Page 374 CHAPTER 19 UART2/3 Figure 19.7-14 Master-slave Communication Flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN2/3 pin as the Set SIN2/3 pin as the serial data input pin. serial data input pin. Set SOT2/3 pin as the Set SOT2/3 pin as the serial data output pin.
Page 375: Lin Communication Function
CHAPTER 19 UART2/3 19.7.7 LIN Communication Function UART2/3 communication with LIN devices is available for both LIN master and LIN slave systems. ■ LIN-master-slave Communication Function The settings shown in the figure below are required to operate UART2/3 in LIN communication mode (operation mode 3).
Page 376: Sample Flowcharts For Uart2/3 In Lin Communication (Operation Mode 3)
CHAPTER 19 UART2/3 19.7.8 Sample Flowcharts for UART2/3 in LIN Communication (Operation Mode 3) This section contains sample flowcharts for UART2/3 in LIN communication. ■ UART2/3 as Master Device Figure 19.7-17 UART2/3 LIN Master Flow Chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting...
Page 377 CHAPTER 19 UART2/3 ■ UART2/3 as Slave Device Figure 19.7-18 UART2/3 LIN Slave Flow Chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 Connection with UART and ICU Reception prohibited ICU interrupt enabled Synch break interrupt enabled...
Page 378: Notes On Using Uart2/3
CHAPTER 19 UART2/3 19.8 Notes on Using UART2/3 Notes on using UART2/3 are given below. ■ Notes on Using UART2/3 ● Enabling operations In UART2/3, the control register (SCR2/3) has TXE (transmission) and RXE (reception) operation enable bits. Both transmission and reception operations must be enabled before the communication starts because they have been disabled as the default value (initial value).
Page 379 CHAPTER 19 UART2/3 ● LIN slave settings Set the baud rate before receiving the first LIN synch break for the slave operation. Otherwise, duration of the synch break can not be correctly checked against the minimum requirement of the LIN specification (13 master bit time and 11 slave bit time).
Page 380 CHAPTER 19 UART2/3...
Page 381: Chapter 20 400 Khz I 2 C Interface
CHAPTER 20 400 kHz I C INTERFACE This section explains the functions and operation of the fast I C interface. 20.1 I C Interface Overview 20.2 I C Interface Registers 20.3 I C Interface Operation 20.4 Programming Flow Charts...
Page 382: I 2 C Interface Overview
CHAPTER 20 400 kHz I C INTERFACE 20.1 C Interface Overview The I C interface is a serial I/O port supporting the Inter IC bus, operating as a master/ slave device on the I C bus. ■ Features • Master/slave transmitting and receiving functions •...
Page 383 CHAPTER 20 400 kHz I C INTERFACE Figure 20.1-1 Block Diagram ICCR C enable ICCR Clock divider 1 2 3 4 5 ... 32 Clock selector Sync Clock divider 2 (by 12) Shift clock generator SCL duty cycle generator IBSR Bus busy Repeated start Bus observer...
Page 384: I 2 C Interface Registers
CHAPTER 20 400 kHz I C INTERFACE 20.2 C Interface Registers This section describes the function of the I C interface registers in detail. ■ I C Interface Registers Figure 20.2-1 I C Interface Registers (1/2) Bus control register (IBCR) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: BER BEIE SCC MSS ACK GCAA INTE...
Page 385 CHAPTER 20 400 kHz I C INTERFACE Figure 20.2-1 I C Interface Registers (2/2) Seven bit slave address mask register (ISMK) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0 0035A7 Initial value 01111111 R/W R/W R/W R/W R/W R/W...
Page 386: Bus Status Register (Ibsr)
CHAPTER 20 400 kHz I C INTERFACE 20.2.1 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • Bus busy detection • Repeated start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication •...
Page 387 CHAPTER 20 400 kHz I C INTERFACE ■ Bus Status Register (IBSR) Contents Table 20.2-1 Function of Each Bit of the Bus Status Register (IBSR) (1 / 2) Bit name Function bit7 This bit indicates the status of the I C bus.
Page 388 CHAPTER 20 400 kHz I C INTERFACE Table 20.2-1 Function of Each Bit of the Bus Status Register (IBSR) (2 / 2) Bit name Function bit1 GCA: This bit indicates detection of a general call address (0x00). General call "0": General call address not received as slave. address bit "1": General call address received as slave.
Page 389: Bus Control Register (Ibcr)
CHAPTER 20 400 kHz I C INTERFACE 20.2.2 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions: • Interrupt enabling flags • Interrupt generation flag • Bus error detection flag • Repeated start condition generation • Master / slave mode selection •...
Page 390 CHAPTER 20 400 kHz I C INTERFACE ■ Bus Control Register (IBCR) Contents Table 20.2-2 Function of Each Bit of the Bus Control Register (IBCR) (1 / 2) Bit name Function bit15 BER: This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. Bus error bit It always reads "1"...
Page 391 CHAPTER 20 400 kHz I C INTERFACE Table 20.2-2 Function of Each Bit of the Bus Control Register (IBCR) (2 / 2) Bit name Function bit11 ACK: This is the acknowledge generation on data byte reception enable bit. It only can be Acknowledge bit changed by the user.
Page 392 CHAPTER 20 400 kHz I C INTERFACE ■ SCC, MSS and INT Bit Competition Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as follows: Next byte transfer and stop condition generation.
Page 393: Ten Bit Slave Address Register (Itba)
CHAPTER 20 400 kHz I C INTERFACE 20.2.3 Ten Bit Slave Address Register (ITBA) This register (ITBAH / ITBAL) designates the ten bit slave address. ■ Ten Bit Slave address Register (ITBA) Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 20.2-4 Configuration of Ten Bit Slave address Register (ITBA) ITBAH (upper) Address:...
Page 394: Ten Bit Address Mask Register (Itmk)
CHAPTER 20 400 kHz I C INTERFACE 20.2.4 Ten Bit Address Mask Register (ITMK) This register contains the ten bit slave address mask and the ten bit slave address enable bit. ■ Ten Bit address Mask Register (ITMK) Figure 20.2-5 Ten Bit address Mask Register (ITMK) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper)
Page 395 CHAPTER 20 400 kHz I C INTERFACE ■ Ten Bit address Mask Register (ITMK) Contents Table 20.2-4 Function of Each Bit of the Ten Bit address Mask Register (ITMK) Bit name Function bit15 ENTB: This bit enables the ten bit slave address (and the acknowledging upon its reception). Enable ten bit Write access to this bit is only possible if the interface is disabled (EN="0"...
Page 396: Seven Bit Slave Address Register (Isba)
CHAPTER 20 400 kHz I C INTERFACE 20.2.5 Seven Bit Slave Address Register (ISBA) This register designates the seven bit slave address. ■ Seven Bit Slave address Register (ISBA) Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 20.2-6 Configuration of Seven Bit Slave address Register (ISBA) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address:...
Page 397 CHAPTER 20 400 kHz I C INTERFACE ■ Seven Bit Slave address Mask Register (ISMK) Contents Table 20.2-6 Function of Each Bit of the Seven Bit Slave address Mask Register Bit name Function bit15 ENSB: This bit enables the seven bit slave address (and the acknowledging upon its reception). Enable seven bit "0": Seven bit slave address disabled slave address bit...
Page 398: Data Register (Idar)
CHAPTER 20 400 kHz I C INTERFACE 20.2.6 Data Register (IDAR) Data Register for the 400 kHz I C Interface. ■ Data Register (IDAR) Figure 20.2-8 Configuration of Data Register (IDAR) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: D7 D6 D5 D4 D3 D2 D1 D0 0035A8...
Page 399: Clock Control Register (Iccr)
CHAPTER 20 400 kHz I C INTERFACE 20.2.7 Clock Control Register (ICCR) The clock control register (ICCR) has the following functions: • Enable test mode • Enable I/O pad noise filters • Enable I C interface operation • Setting the serial clock frequency ■...
Page 400 CHAPTER 20 400 kHz I C INTERFACE ■ Clock Control Register (ICCR) Contents Table 20.2-8 Function of Each Bit of the Clock Control Register Bit name Function bit15 Undefined This bit always returns "0" during reading. bit14 NSF: This bit enables the noise filters built into the SDA and SCL I/O pads. I/O pad noise The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and filter enable bit...
Page 401 CHAPTER 20 400 kHz I C INTERFACE ■ Clock Prescaler Settings The calculation formula for CS0 to CS4 is determined as follows: φ Bitrate = n>0 : machine clock, Noise filter disabled n 12 + 16 φ Bitrate = n>0 : machine clock, Noise filter enabled n 12 + 17 Table 20.2-9 Prescaler Settings...
Page 402: I 2 C Interface Operation
CHAPTER 20 400 kHz I C INTERFACE 20.3 C Interface Operation The I C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines, enabling wired logic applications.
Page 403 CHAPTER 20 400 kHz I C INTERFACE Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits. The received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK register (this bit is valid if the AAS bit is set only).
Page 404 CHAPTER 20 400 kHz I C INTERFACE ■ Acknowledgement Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be used to select whether to send an acknowledgment when data bytes are received. When data is send in slave mode (read access from another master), if no acknowledgement is received from the master, the TRX bit is set to "0"...
Page 405: Programming Flow Charts
CHAPTER 20 400 kHz I C INTERFACE 20.4 Programming Flow Charts Each programming flow charts for the 400 kHz I C interface is shown below. ■ Programming Flow Charts Figure 20.4-1 Example of Slave Addressing and Sending Data Addressing a 7 bit slave Sending data Start Start...
Page 406 CHAPTER 20 400 kHz I C INTERFACE Figure 20.4-2 Example of Receiving Data Start Address slave for read Clear ACK bit in IBCR if it’s the last byte to read from slave; INT := 0 INT=1? Bus error BER=1? reenable IF Last byte transferred? Transfer End...
Page 407: Chapter 21 Serial I/O
CHAPTER 21 SERIAL I/O This chapter explains the functions and operations of the serial I/O. 21.1 Outline of Serial I/O 21.2 Serial I/O Registers 21.3 Serial I/O Prescaler (CDCR) 21.4 Serial I/O Operation...
Page 408: Outline Of Serial I/O
CHAPTER 21 SERIAL I/O 21.1 Outline of Serial I/O The serial I/O interface operates in two modes: • Internal shift clock mode: Data is transferred in synchronization with the internal clock. • External shift clock mode: Data is transferred in synchronization with the clock supplied via the external pin (SCK4).
Page 409: Serial I/O Registers
CHAPTER 21 SERIAL I/O 21.2 Serial I/O Registers The serial I/O has the following two registers: • Serial mode control status register (SMCS) • Serial data register (SDR) ■ Serial I/O Registers Figure 21.2-1 Serial I/O Registers Serial mode control status register (SMCS) bit15 bit14 bit13...
Page 410: Serial Mode Control Status Register (Smcs)
CHAPTER 21 SERIAL I/O 21.2.1 Serial Mode Control Status Register (SMCS) The serial mode control status register (SMCS) controls the serial I/O transfer mode. ■ Upper Byte of Serial Mode Control Status Register (SMCS) Figure 21.2-2 Configuration of the Serial Mode Control Status Register (Upper Byte) bit15 bit14 bit13...
Page 411 CHAPTER 21 SERIAL I/O ■ Lower Byte of Serial Mode Control Status Register (SMCS) Figure 21.2-3 Configuration of the Serial Mode Control Status Register (Lower Byte) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address : Initial value MODE SCOE 00002C XXXX0000 SCOE...
Page 412 CHAPTER 21 SERIAL I/O ■ Bit Functions of Serial Mode Control Status Register (SMCS) Table 21.2-1 Bit Functions of Serial Mode Control Status Register Bit No. Name Function bit15 SMD0 to SMD2: See Table 21.2-2. Shift clock mode bit13 selection bits bit12 SIE: This bit controls the serial I/O interrupt request as shown above.This bit is initialized to "0"...
Page 413 CHAPTER 21 SERIAL I/O ■ Shift Clock Selection The Shift Clock Mode Selection bits are used to select the serial shift clock mode, as shown in Table 21.2- 2. The second part is related to the Serial I/O prescaler register (CDCR). For details, see Section "21.3 Serial I/O Prescaler (CDCR)".
Page 414: Serial Data Register (Sdr)
CHAPTER 21 SERIAL I/O 21.2.2 Serial Data Register (SDR) This serial data register stores the serial I/O transfer data. During transfer, the SDR must not be read or written to. ■ Serial Data Register (SDR) Figure 21.2-4 Configuration of Serial Data Register (SDR) bit7 bit6 bit5...
Page 415: Serial I/O Prescaler (Cdcr)
CHAPTER 21 SERIAL I/O 21.3 Serial I/O Prescaler (CDCR) The Serial I/O Prescaler provides the shift clock for the Serial I/O. The operation clock for the Serial I/O is obtained by dividing the machine clock. The Serial I/O is designed so that a constant baud rate can be obtained for a variety of machine clocks by the use of the communication prescaler.
Page 416: Serial I/O Operation
CHAPTER 21 SERIAL I/O 21.4 Serial I/O Operation The extended serial I/O consists of the serial mode control status register (SMCS) and shift register (SDR), and is used for input and output of 8-bit serial data. ■ Serial I/O Operation The bits in the shift register are serially output via the serial output pin (SOT4 pin) at the falling edge of the serial shift clock (external clock or internal clock).
Page 417: Shift Clock
CHAPTER 21 SERIAL I/O 21.4.1 Shift Clock There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit. ■...
Page 418: Serial I/O Operation
CHAPTER 21 SERIAL I/O 21.4.2 Serial I/O Operation There are four serial I/O operation statuses: • STOP • Halt • SDR R/W standby • Transfer ■ Serial I/O Operation ● STOP The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift counter is initialized, and "0"...
Page 419 CHAPTER 21 SERIAL I/O Figure 21.4-1 Extended I/O Serial Interface Operation Transitions Reset STOP=0 & STRT=0 End of transfer STOP STRT=0, BUSY=0 STRT=0, BUSY=0 STOP=1 MODE=0 MODE=0 STOP=0 & & STOP=0 STOP=1 STOP=1 STOP=0 STRT=1 & & STRT=1 Transfer Serial data register R/W standby MODE=1 &...
Page 420: Shift Operation Start/Stop Timing
CHAPTER 21 SERIAL I/O 21.4.3 Shift Operation Start/Stop Timing To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS. The system may stop the shift operation at the end of transfer or when "1" is set in the STOP bit.
Page 421 CHAPTER 21 SERIAL I/O ● External shift clock mode with instruction shift (LSB first) Figure 21.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift) SCK="0"in PDR SCK="0" in PDR SCK4 SCK="1" in PDR (Transfer end) STRT If MODE=0 BUSY DO7 (Data maintained) SOT4...
Page 422 CHAPTER 21 SERIAL I/O Figure 21.4-7 Serial Data I/O Shift Timing ❍ LSB first (When the BDS bit is "0") SCK4 SIN Input SIN4 SOT Output SOT4 ❍ MSB first (When the BDS bit is "1") SCK4 SIN Input SIN4 SOT Output SOT4...
Page 423: Interrupt Function Of The Extended Serial I/O Interface
CHAPTER 21 SERIAL I/O 21.4.4 Interrupt Function of the Extended Serial I/O Interface This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU.
Page 424 CHAPTER 21 SERIAL I/O...
Page 425: Chapter 22 Can Controller
CHAPTER 22 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. CAUTION: Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and MB90V390HA. The problem is fixed on MB90F946A, MB90947A, MB90F947A, MB90F949A, MB90V390HB.
Page 426: Features Of Can Controller
CHAPTER 22 CAN CONTROLLER 22.1 Features of CAN Controller The CAN controller is a module built into a 16-bit microcontroller (F MC-16LX). The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■...
Page 427: Block Diagram Of Can Controller
CHAPTER 22 CAN CONTROLLER 22.2 Block Diagram of CAN Controller Figure 22.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 22.2-1 Block Diagram of CAN Controller TQ (Operating clock) MC-16LX bus Prescaler Clock Bit timing generation SYNC, TSEG1, TSEG2 1 to 64 frequency division...
Page 428: List Of Overall Control Registers
CHAPTER 22 CAN CONTROLLER 22.3 List of Overall Control Registers Table 22.3-1 lists overall control registers. ■ List of Overall Control Registers Table 22.3-1 List of Overall Registers (1 / 2) Address Register Abbreviation Access Initial value CAN1 000080 Message buffer BVALR 00000000 00000000 valid register...
Page 429 CHAPTER 22 CAN CONTROLLER Table 22.3-1 List of Overall Registers (2 / 2) Address Register Abbreviation Access Initial value CAN1 003908 IDE register IDER XXXXXXXX XXXXXXXX 003909 00390A Transmit RTR TRTRR 00000000 00000000 register 00390B 00390C Remote frame receive RFWTR XXXXXXXX XXXXXXXX waiting 00390D...
Page 430: List Of Message Buffers (Id Registers)
CHAPTER 22 CAN CONTROLLER 22.4 List of Message Buffers (ID Registers) Table 22.4-1 lists message buffers (ID registers). ■ List of Message Buffers (ID Registers) Table 22.4-1 List of Message Buffers (ID Registers) (1 / 3) Address Register Abbreviation Access Initial value CAN1 003800...
Page 431 CHAPTER 22 CAN CONTROLLER Table 22.4-1 List of Message Buffers (ID Registers) (2 / 3) Address Register Abbreviation Access Initial value CAN1 003834 ID register 5 IDR5 XXXXXXXX XXXXXXXX 003835 003836 XXXXX--- XXXXXXXX 003837 003838 ID register 6 IDR6 XXXXXXXX XXXXXXXX 003839 00383A XXXXX--- XXXXXXXX...
Page 432 CHAPTER 22 CAN CONTROLLER Table 22.4-1 List of Message Buffers (ID Registers) (3 / 3) Address Register Abbreviation Access Initial value CAN1 003850 ID register 12 IDR12 XXXXXXXX XXXXXXXX 003851 003852 XXXXX--- XXXXXXXX 003853 003854 ID register 13 IDR13 XXXXXXXX XXXXXXXX 003855 003856 XXXXX--- XXXXXXXX...
Page 433: List Of Message Buffers (Dlc Registers And Data Registers)
CHAPTER 22 CAN CONTROLLER 22.5 List of Message Buffers (DLC Registers and Data Registers) Table 22.5-1 lists message buffers (DLC registers) and message buffers (data registers). ■ List of Message Buffers (DLC Registers and Data Registers) Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (1 / 3) Address Register Abbreviation...
Page 434 CHAPTER 22 CAN CONTROLLER Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (2 / 3) Address Register Abbreviation Access Initial value CAN1 003878 DLC register 12 DLCR12 ----XXXX 003879 00387A DLC register 13 DLCR13 ----XXXX 00387B 00387C DLC register 14 DLCR14 ----XXXX...
Page 435 CHAPTER 22 CAN CONTROLLER Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (3 / 3) Address Register Abbreviation Access Initial value CAN1 0038C8 Data register 9 DTR9 XXXXXXXX (8 bytes) 0038CF XXXXXXXX 0038D0 Data register 10 (8 DTR10 XXXXXXXX bytes)
Page 436: Classifying The Can Controller Registers
CHAPTER 22 CAN CONTROLLER 22.6 Classifying the CAN Controller Registers There are three types of CAN controller registers: • Overall control registers • Message buffer control registers • Message buffers ■ Overall Control Registers The overall control registers are the following four registers: •...
Page 437: Control Status Register (Csr)
CHAPTER 22 CAN CONTROLLER 22.6.1 Control Status Register (CSR) Control status register (CSR) is prohibited from executing any bit manipulation instructions (read-modify-write instructions). ■ Control Status Register (CSR) (Lower) Figure 22.6-1 Configuration of the Control Status Register (CSR) (Lower Byte) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: CAN1: 003900...
Page 438 CHAPTER 22 CAN CONTROLLER ■ Control Status Register (CSR) (Lower) Contents Table 22.6-1 Function of Each Bit of the Control Status Register (CSR) (Lower) Bit name Function bit7 TOE: Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the Transmit output CAN controller.
Page 439 CHAPTER 22 CAN CONTROLLER ■ Control Status Register (CSR) (Upper) Figure 22.6-2 Configuration of the Control Status Register (CSR) (Upper Byte) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: Initial value 00XXX000 CAN1: 003901 Node status bits Error active Warning (error active) Error passive Bus off...
Page 440 CHAPTER 22 CAN CONTROLLER ■ Control Status Register (CSR-upper) Contents Table 22.6-2 Function of Each Bit of the Control Status Register (Upper) Bit Name Function bit15 This bit indicates whether a message is being transmitted. Transmit status 0: Message not being transmitted 1: Message being transmitted This bit is "0"...
Page 441 CHAPTER 22 CAN CONTROLLER Figure 22.6-3 Node Status Transition Diagram Hardware reset REC: Receive error counter TEC: Transmit error counter Error active After 0 has been writtentothe HALT bit of REC >= 96 the register (CSR), continuous 11-bit "H" TEC >= 96 levels (recessive bits) are input 128 times to the receive input pin (RX).
Page 442: Bus Operation Stop Bit (Halt = 1)
CHAPTER 22 CAN CONTROLLER 22.6.2 Bus Operation Stop Bit (HALT = 1) The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status ■ Conditions for Setting Bus Operation Stop (HALT=1) There are three conditions for setting bus operation stop (HALT = 1): •...
Page 443: Last Event Indicator Register (Leir)
CHAPTER 22 CAN CONTROLLER 22.6.3 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to "1", other bits are set to "0"s. ■...
Page 444 CHAPTER 22 CAN CONTROLLER ■ Last Event Indicator Register (LEIR) Contents Table 22.6-4 Function of Each Bit of the Last Event Indicator Register Bit name Function bit7 NTE: When this bit is "1", node status transition is the last event. Node status This bit is set to "1"...
Page 445: Receive And Transmit Error Counters (Rtec)
CHAPTER 22 CAN CONTROLLER 22.6.4 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Receive and Transmit Error Counters (RTEC) Figure 22.6-5 Configuration of the Receive and Transmit Error Counters (RTEC) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 446: Bit Timing Register (Btr)
CHAPTER 22 CAN CONTROLLER 22.6.5 Bit Timing Register (BTR) Bit timing register (BTR) stores the prescaler and bit timing setting. ■ Bit Timing Register (BTR) Figure 22.6-6 Configuration of the Bit Timing Register (BTR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper) CAN1: 003907 TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0...
Page 447 CHAPTER 22 CAN CONTROLLER ■ Prescaler Settings The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure 22.6-7 and Figure 22.6-8 respectively. Figure 22.6-7 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2...
Page 448: Message Buffer Valid Register (Bvalr)
CHAPTER 22 CAN CONTROLLER 22.6.6 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. ■ Message Buffer Valid Register (BVALR) Figure 22.6-9 Configuration of the Message Buffer Valid Register (BVALR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper)
Page 449: Ide Register (Ider)
CHAPTER 22 CAN CONTROLLER 22.6.7 IDE Register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. ■ IDE Register (IDER) Figure 22.6-10 Configuration of the IDE Register (IDER) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper) IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8 CAN1: 003909...
Page 450: Transmission Request Register (Treqr)
CHAPTER 22 CAN CONTROLLER 22.6.8 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. ■ Transmission Request Register (TREQR) Figure 22.6-11 Configuration of the Transmission Request Register (TREQR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper) TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8...
Page 451: Transmission Rtr Register (Trtrr)
CHAPTER 22 CAN CONTROLLER 22.6.9 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). ■ Transmission RTR Register (TRTRR) Figure 22.6-12 Configuration of the Transmission RTR Register (TRTRR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper) CAN1: 00390B TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8...
Page 452: Remote Frame Receiving Wait Register (Rfwtr)
CHAPTER 22 CAN CONTROLLER 22.6.10 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) stores the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR register (TRTRR) is "0").
Page 453: Transmission Cancel Register (Tcanr)
CHAPTER 22 CAN CONTROLLER 22.6.11 Transmission Cancel Register (TCANR) When "1" is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes "0". Writing "0" to TCANx is ignored. This is a write-only register and its read value is always "0".
Page 454: Transmission Complete Register (Tcr)
CHAPTER 22 CAN CONTROLLER 22.6.12 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes "1". If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt occurs. ■ Transmission Complete Register (TCR) Figure 22.6-15 Configuration of the Transmission Complete Register (TCR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 455: Transmission Interrupt Enable Register (Tier)
CHAPTER 22 CAN CONTROLLER 22.6.13 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is "1"). ■...
Page 456: Reception Complete Register (Rcr)
CHAPTER 22 CAN CONTROLLER 22.6.14 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes "1". If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt occurs. ■ Reception Complete Register (RCR) Figure 22.6-17 Configuration of the Reception Complete Register (RCR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 457: Remote Request Receiving Register (Rrtrr)
CHAPTER 22 CAN CONTROLLER 22.6.15 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the same time as RCx setting to "1"). ■ Remote Request Receiving Register (RRTRR) Figure 22.6-18 Configuration of the Remote Request Receiving Register (RRTRR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (upper)
Page 458: Receive Overrun Register (Rovrr)
CHAPTER 22 CAN CONTROLLER 22.6.16 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is "1" when completing storing of a received message in the message buffer (x), ROVRx becomes "1", indicating that reception has overrun. ■ Receive Overrun Register (ROVRR) Figure 22.6-19 Configuration of the Receive Overrun Register (ROVRR) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 459: Reception Interrupt Enable Register (Rier)
CHAPTER 22 CAN CONTROLLER 22.6.17 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is "1"). ■...
Page 460: Acceptance Mask Select Register (Amsr)
CHAPTER 22 CAN CONTROLLER 22.6.18 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID’s. ■ Acceptance Mask Select Register (AMSR) Figure 22.6-21 Configuration of the acceptance Mask Select Register (AMSR) Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Byte 0...
Page 461 CHAPTER 22 CAN CONTROLLER To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "22.15 Precautions when Using CAN Controller".
Page 462: Acceptance Mask Registers 0 And 1 (Amr0 And Amr1)
CHAPTER 22 CAN CONTROLLER 22.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
Page 463 CHAPTER 22 CAN CONTROLLER Figure 22.6-23 Configuration of the acceptance Mask Register 1 (AMR1) Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Byte 0 CAN1: 003918 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Initial value XXXXXXXX R/W R/W R/W R/W R/W R/W Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8...
Page 464: Message Buffers
CHAPTER 22 CAN CONTROLLER 22.6.20 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ● The message buffer (x) is used both for transmission and reception. ●...
Page 465: Id Register X (X = 0 To 15) (Idrx)
CHAPTER 22 CAN CONTROLLER 22.6.21 ID Register x (x = 0 to 15) (IDRx) ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x). ■ ID Register x (x = 0 to 15) (IDRx) Figure 22.6-24 Configuration of the ID Registers (IDRx) Address: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...
Page 466 CHAPTER 22 CAN CONTROLLER Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
Page 467: Dlc Register X (X = 0 To 15) (Dlcrx)
CHAPTER 22 CAN CONTROLLER 22.6.22 DLC Register x (x = 0 to 15) (DLCRx) DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x. Figure 22.6-25 Configuration of the DLC Registers (DLCRx) Address: (lower) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value...
Page 468: Data Register X (X = 0 To 15) (Dtrx)
CHAPTER 22 CAN CONTROLLER 22.6.23 Data Register x (x = 0 to 15) (DTRx) Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame.
Page 469 CHAPTER 22 CAN CONTROLLER ● Sets transmitted message data (any of 0 to 8 bytes) Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ● Stores received message data Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined.
Page 470: Transmission Of Can Controller
CHAPTER 22 CAN CONTROLLER 22.7 Transmission of CAN Controller When "1" is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and TCx of the transmission complete register (TCR) becomes "0". ■...
Page 471 CHAPTER 22 CAN CONTROLLER ■ Completing Transmission of the CAN Controller When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission complete register (TCR) becomes "1". If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is "1"), an interrupt occurs.
Page 472: Reception Of Can Controller
CHAPTER 22 CAN CONTROLLER 22.8 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is "0").
Page 473 CHAPTER 22 CAN CONTROLLER Figure 22.8-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to all bits compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to all bits mask.
Page 474 CHAPTER 22 CAN CONTROLLER ■ Completing Reception RCx of the reception complete register (RCR) becomes "1" after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself.
Page 475: Reception Flowchart Of Can Controller
CHAPTER 22 CAN CONTROLLER 22.9 Reception Flowchart of CAN Controller Figure 22.9-1 shows a reception flowchart of the CAN controller. ■ Reception Flowchart of the CAN Controller Figure 22.9-1 Reception Flowchart of the CAN Controller Detection of start of data frame or remote frame (SOF) Is any message buffer (x) passing to the acceptance filter found?
Page 476: 22.10 How To Use The Can Controller
CHAPTER 22 CAN CONTROLLER 22.10 How to Use the CAN Controller The following settings are required to use the CAN controller: • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ CAUTION: Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and MB90V390HA.
Page 477 CHAPTER 22 CAN CONTROLLER ■ Setting Low-power Consumption Mode To set the F MC-16LX in a low-power consumption mode (stop and timebase timer), write "1" to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1).
Page 478: Procedure For Transmission By Message Buffer (X)
CHAPTER 22 CAN CONTROLLER 22.11 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to activate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ●...
Page 479 CHAPTER 22 CAN CONTROLLER ● Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable register (TIER) to "1". When not generating a transmission complete interrupt, set TIEx to "0". ● Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
Page 480: Procedure For Reception By Message Buffer (X)
CHAPTER 22 CAN CONTROLLER 22.12 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for Reception by Message Buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
Page 481 CHAPTER 22 CAN CONTROLLER Figure 22.12-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A: = ROVRx ROVRx := 0 A = 0? RCx := 0...
Page 482: 22.13 Setting Configuration Of Multi-Level Message Buffer
CHAPTER 22 CAN CONTROLLER 22.13 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU.
Page 483 CHAPTER 22 CAN CONTROLLER Figure 22.13-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 . . . AM28 to AM18 Select AMR0. AMS0 0000 1111 111 RC15, RC14, RC13 ID28 to ID18 ..
Page 484: 22.14 Setting The Can Direct Mode Register
CHAPTER 22 CAN CONTROLLER 22.14 Setting the CAN Direct Mode Register The MB90945 series provides a clock modulator for the system clock. Since the CAN controller is not able to operate with a modulated clock, the unmodulated clock is provided to the CAN controller independently from the clock modulator settings. ■...
Page 485: 22.15 Precautions When Using Can Controller
CHAPTER 22 CAN CONTROLLER 22.15 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"...
Page 486 CHAPTER 22 CAN CONTROLLER...
Page 487: Chapter 23 Address Match Detection Function
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION This chapter explains the functions and operations of the address match detection function. 23.1 Outline of the Address Match Detection Function 23.2 Registers of the Address Match Detection Function 23.3 Operation of the Address Match Detection Function 23.4 Example of the Address Match Detection Function...
Page 488: Outline Of The Address Match Detection Function
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.1 Outline of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01 Consequently, the CPU executes the INT9 instruction when executing a specified instruction.
Page 489: Registers Of The Address Match Detection Function
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0 to PADR2) • Program address detection control status register (PACSR0) ■...
Page 490 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION ■ Program address Detection Control Status Register (PACSR0) The program address detection control status register (PACSR0) controls the operation of the address detection function. Figure 23.2-2 Program address Detection Control Status Registers (PACSR0) Address: bit7 bit6 bit5...
Page 491: Operation Of The Address Match Detection Function
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.3 Operation of the Address Match Detection Function If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine.
Page 492: Example Of The Address Match Detection Function
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION 23.4 Example of the Address Match Detection Function Figure 23.4-1 shows a system configuration example of the address match detection function. Table 23.4-1 lists the EEPROM memory map. ■ System Configuration Example of the address Match Detection Function Figure 23.4-1 System Configuration Example of the address Match Detection Function EEPROM MC16LX...
Page 493 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION ● When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to EEPROM. ● Reset sequence The MCU reads the value of EEPROM after reset.
Page 494 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION ■ Example of Program Patch Processing Figure 23.4-2 Example of Program Patch Processing 000000 Correction program Program address detection register PROM Correction program byte number Program address detection setting Interrutp generation address (reset sequence) Correction program Abnormal program FFFFFF...
Page 495 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION Figure 23.4-3 Flow of Program Patch Processing Reset Reads 00 of EEPROM INT9 0000 (EEPROM)=0 To patch program JMP 000400 Read address 0001 to 0003 (EEPROM) Execute patch program PADR0 (MCU) 000400 to 000480 Read patch program Terminate patch program JMP FF0050...
Page 496 CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION...
Page 497: Chapter 24 Rom Mirroring Module
CHAPTER 24 ROM MIRRORING MODULE This chapter explains the ROM mirroring module. 24.1 Outline of ROM Mirroring Module 24.2 ROM Mirroring Register (ROMM)
Page 498: Outline Of Rom Mirroring Module
CHAPTER 24 ROM MIRRORING MODULE 24.1 Outline of ROM Mirroring Module The ROM Mirroring module switches whether to mirror the image of the FF bank of the ROM to the 00 bank. ■ Block Diagram of ROM Mirroring Module Figure 24.1-1 Block Diagram of ROM Mirroring Module MC-16LX BUS ROM Mirrroring Register Address Area...
Page 499: Rom Mirroring Register (Romm)
CHAPTER 24 ROM MIRRORING MODULE 24.2 ROM Mirroring Register (ROMM) Do not access the ROM mirroring register (ROMM) when addresses 004000 to 00FFFF are being accessed. ■ ROM Mirroring Register (ROMM) Figure 24.2-1 Configuration of the ROM Mirroring Register (ROMM) Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value...
Page 500 CHAPTER 24 ROM MIRRORING MODULE...
Page 501: Chapter 25 1M/2M/3M-Bit Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY This chapter explains the functions and operations of the 1M/2M/3M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer •...
Page 502: Overview Of 1M/2M/3M-Bit Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.1 Overview of 1M/2M/3M-Bit Flash Memory The 1M/2M/3M-bit flash memory is mapped to the F9/FC/FE to FF bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory.
Page 503: Block Diagram Of The Entire Flash Memory And Sector Configuration Of The Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 25.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 25.2-2 shows the sector configuration of the 1M-bit flash memory and Figure 25.2-3 shows the sector configuration of the 2M-bit flash memory and Figure 25.2-4 shows the sector configuration of the 3M-bit flash memory.
Page 504 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ■ Sector Configuration of the 1M-bit Flash Memory Figure 25.2-2 shows the sector configuration of the 1M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. Figure 25.2-2 Sector Configuration of the 1M-bit Flash Memory MB90F947(A) Programmer address* CPU address...
Page 505 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ■ Sector Configuration of the 2M-bit Flash Memory Figure 25.2-3 shows the sector configuration of the 2M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. Figure 25.2-3 Sector Configuration of the 2M-bit Flash Memory MB90F949(A) Programmer address* CPU address...
Page 506 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ■ Sector Configuration of the 3M-bit Flash Memory Figure 25.2-4 shows the sector configuration of the 3M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. Figure 25.2-4 Sector Configuration of the 3M-bit Flash Memory MB90F946A Programmer address* CPU address...
Page 507: Write/Erase Modes
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.3 Write/Erase Modes The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus.
Page 508 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY Table 25.3-1 Flash Memory Control Signals MB90F947(A)/MB90F949(A)/MB90F946A MBM29LV200 Pin number Normal function Flash memory mode AQ16 AQ17 AQ18 BYTE BYTE RY/BY RY/BY 18 to 21 P40 to P43 AQ8 to AQ11 A7 to A10 22, 23 P46, P47 AQ12, AQ13 A11, A12...
Page 509: Flash Memory Control Status Register (Fmcs)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.4 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 25.4-1 Flash Memory Control Status Register (FMCS) bit7 bit6...
Page 510 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY [bit4] RDY (ready) This bit enables flash memory write/erase. Flash memory write/erase is disabled while this bit is "0". However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is "0". •...
Page 511: Starting The Flash Memory Automatic Algorithm
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/reset, Write, and Chip erase. Control of suspend and restart is enabled for sector erase. ■...
Page 512 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY The Auto-select command shown in Table 25.5-1 is used to know the state of sector protection. When using the Auto-select command, set the address as follows. Table 25.5-2 Address Setting at Auto-select AQ13 to AQ18 DQ7 to DQ0 Sector protection Sector Address...
Page 513: Confirming The Automatic Algorithm Execution State
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences.
Page 514 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY Table 25.6-2 Hardware Sequence Flag Functions State → → → → → → State Write Write completed (write Toggle change for address specified) DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 normal → → Toggle Toggle operation → →...
Page 515: Data Polling Flag (Dq7)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data Polling Flag (DQ7) Table 25.6-3 and Table 25.6-4 list the state transitions of the data polling flag. Table 25.6-3 Data Polling Flag State Transitions (State Change for Normal Operation) Sector erase Sector erase...
Page 516 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased.
Page 517: Toggle Bit Flag (Dq6)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 25.6-5 and Table 25.6-6 list the state transitions of the toggle bit flag.
Page 518: Timing Limit Exceeded Flag (Dq5)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 25.6-7 and Table 25.6-8 list the state transitions of the timing limit exceeded flag.
Page 519: Sector Erase Timer Flag (Dq3)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started.
Page 520 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ● Read access during sector erase Read-access during execution of sector erase suspend causes the flash memory to output "1" if the address specified by the address signal belongs to the sector being erased. If this address does not belong to the sector being erased, the flash memory outputs bit3 (DATA:3) of the corresponding memory value.
Page 521: Toggle Bit-2 Flag (Dq2)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.6.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. ■ Toggle Bit-2 Flag (DQ2) Table 25.6-11 and Table 25.6-12 list the state transitions of the toggle bit flag. Table 25.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation) Sector erase Sector erase...
Page 522 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ● While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit2 (DATA: 2) to the location indicated by the address.
Page 523: Detailed Explanation Of Writing To And Erasing Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■...
Page 524: Setting The Read/Reset State
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/Reset State The flash memory can be set to the read/reset state by sending the read/reset command in the command sequence table (see "■...
Page 525: Writing Data
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see "■...
Page 526 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY Figure 25.7-1 Example of the Flash Memory Write Procedure Start writing FMCS: WE (bit 5) Enable flash memory write Write command sequence ← XXAA (1) FxAAAA ← XX55 (2) Fx5554 ← XXA0 (3) FxAAAA (4) Write address ← Write data Read internal address Next address Data...
Page 527: Erasing All Data (Erasing Chips)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the chip erase command to erase all data in the flash memory. ■ Erasing All Data in the Flash Memory (Erasing Chips) All data can be erased from the flash memory by sending the chip erase command in the command sequence table (see "■...
Page 528: Erasing Optional Data (Erasing Sectors)
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.4 Erasing Optional Data (Erasing Sectors) This section describes the procedure for issuing the sector erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. ■...
Page 529 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY Figure 25.7-2 Example of the Flash Memory Sector Erase Procedure Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence ← (1) FxAAAA XXAA ← (2) Fx5554 XX55 ← (3) FxAAAA XX80 ←...
Page 530: Suspending Sector Erase
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.5 Suspending Sector Erase This section describes the procedure for issuing the sector erase suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending Erasing of Flash Memory Sectors Erasing of flash memory sectors can be suspended by sending the sector erase suspend command in the command sequence table (see "■...
Page 531: Restarting Sector Erase
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.7.6 Restarting Sector Erase This section describes the procedure for issuing the sector erase restart command to restart suspended erasing of flash memory sectors. ■ Restarting Erasing of Flash Memory Sectors Suspended erasing of flash memory sectors can be restarted by sending the sector erase restart command in the command sequence table (see "■...
Page 532: Notes On Using 1M/2M/3M-Bit Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.8 Notes on Using 1M/2M/3M-Bit Flash Memory This section contains notes on using 1M/2M/3M-bit flash memory. ■ Notes on Using Flash Memory ● Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum "L"...
Page 533 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ● Applying V Applying V required for the sector protect operation should always be started and terminated when the supply voltage is on.
Page 534: Reset Vector Address In Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.9 Reset Vector Address in Flash Memory The MB90F947(A), MB90F949(A), MB90F946A support a hard-wired reset vector. When the addresses FFFFDC to FFFFDF are accessed for reading data in internal vector mode, the values that have been determined by the hard-wired logic in advance are read.
Page 535: 25.10 Example Of Programming 1M/2M/3M-Bit Flash Memory
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY 25.10 Example of Programming 1M/2M/3M-Bit Flash Memory This section presents a programming example of 1M/2M/3M-bit flash memory. ■ Programming Example of 1M/2M/3M-bit Flash Memory Flash memory sample program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------------------- ;2M/3M-bit-FLASH test program ;1: Transmits the program (address: FF8000H, sector: SA6) from FLASH to RAM (address: 001500H).
Page 536 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ;///////////////////////////////////////////////////////////// ;Main program (FFA000H) ;///////////////////////////////////////////////////////////// CODE CSEG START: ///////////////////////////////////////////////////// Initialization ///////////////////////////////////////////////////// CKSCR,#0BAH ;3-multiple setting RP,#0 A,#!STA_T SSB,A MOVW A,#STA_T MOVW SP,A ROMM,#00H ;Mirror OFF PDR0,#00H ;For error check DDR0,#0FFH PDR1,#00H ;Port for data input DDR1,#00H PDR2,#00H ;Port for data output DDR2,#0FFH...
Page 537 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ;//////////////////////////////////////////////// ;Write (SA1) ;//////////////////////////////////////////////// A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW...
Page 538 CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY /////////////////////////////////////// Erase termination check (FMCS-RDY) /////////////////////////////////////// NTOE MOVW A,FMCS A,#10H ;Extraction of FMCS RDY bit (bit 4) ;End of sector erase? FMCS,#00H ;FLASH erase mode release RETP ;Return to the main program ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR FMCS,#00H ;FLASH mode release...
Page 539: Chapter 26 Examples Of Mb90F947 Synchronous Serial Programming Connection
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION This chapter provides examples of F MC-16LX MB90F947 synchronous serial programming connection. 26.1 Basic Configuration of MB90F947 Synchronous Serial Programming Connection 26.2 Example of Synchronous Serial Programming Connection (User Power Supply Used) 26.3 Example of Synchronous Serial Programming Connection (Power Supplied from the Programmer) 26.4 Example of Minimum Connection to the Flash Microcomputer...
Page 540: Basic Configuration Of Mb90F947 Synchronous Serial Programming Connection
26.1 Basic Configuration of MB90F947 Synchronous Serial Programming Connection The MB90F947 supports flash ROM serial onboard programming (Fujitsu standard). This section describes the specifications. ■ Basic Configuration of MB90F947 Synchronous Serial Programming Connection The AF220/AF210/AF120/AF110 flash microcomputer programmer from Yokogawa Digital Computer Corporation is used for Fujitsu standard serial onboard programming.
Page 541 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION Table 26.1-1 Pins Used for Fujitsu Standard Synchronous Serial Onboard Programming Function Additional information MD2, MD1 Mode pins Controls programming mode from the flash microcomputer programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency.
Page 542 AZ221 PC/AT RS232C cable for programmer AZ210 Standard target probe (a) with a 1 m cable FF201 Fujitsu F MC-16LX flash microcomputer control module AZ290 Remote controller 2 Mbytes PC card (optional) for flash memory sizes up to 128 Kbytes...
Page 543 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION ■ Oscillating Clock Frequency and Serial Clock Input Frequency The equation listed below can be used to calculate the serial clock frequencies that can be used for the MB90F947. Set an appropriate serial clock input frequency in the flash microcomputer programmer according to the oscillating clock frequency in use.
Page 544: Example Of Synchronous Serial Programming Connection (User Power Supply Used)
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION 26.2 Example of Synchronous Serial Programming Connection (User Power Supply Used) Figure 26.2-1 is an example of a synchronous serial programming connection for internal vector modes (single-chip mode) when the user power supply is used. The value "1"...
Page 545 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming.
Page 546: Example Of Synchronous Serial Programming Connection (Power Supplied From The Programmer)
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION 26.3 Example of Synchronous Serial Programming Connection (Power Supplied from the Programmer) Figure 26.3-1 is an example of a synchronous serial programming connection for internal vector modes (single-chip mode) when power is supplied from the programmer. The value "1"...
Page 547 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming.
Page 548: Example Of Minimum Connection To The Flash Microcomputer Programmer (User Power Supply Used)
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION 26.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) Figure 26.4-1 is an example of the minimum connection to the flash microcomputer programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110.
Page 549 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming.
Page 550: Example Of Minimum Connection To The Flash Microcomputer Programmer (Power Supplied From The Programmer)
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION 26.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer) Figure 26.5-1 is an example of the minimum connection to the flash microcomputer programmer when power is supplied from the Programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110.
Page 551 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial programming.
Page 552 CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION...
Page 553: Appendix
APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A I/O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors...
Page 554: Appendix A I/O Maps
APPENDIX A I/O Maps APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks. ■ I/O Maps Table A-1 I/O Map (1 / 5) Address Register Abbreviation Access Peripheral Initial value 000000 Port data register (For port 0) PDR0 Port 0...
Page 555 APPENDIX A I/O Maps Table A-1 I/O Map (2 / 5) Address Register Abbreviation Access Peripheral Initial value 000016 Port direction register (For port 6) DDR6 Port 6 00000000 000017 Reserved 000018 Port direction register (For port 8) DDR8 Port 8 XXXXXX00 000019 Port direction register (For port 9)
Page 556 APPENDIX A I/O Maps Table A-1 I/O Map (3 / 5) Address Register Abbreviation Access Peripheral Initial value 000038 PPG0 operation mode control PPGC0 16-bit Programable 0X000XX1 register Pulse Generator 0/1 000039 PPG1 operation mode control PPGC1 0X000001 register 00003A PPG0 and PPG1 clock select PPG01 000000XX...
Page 557 APPENDIX A I/O Maps Table A-1 I/O Map (4 / 5) Address Register Abbreviation Access Peripheral Initial value 00004C PPGA operation mode control PPGCA 16-bit Programable 0X000XX1 register Pulse Generator A/B 00004D PPGB operation mode control PPGCB 0X000001 register 00004E PPGA and PPGB clock select PPGAB 000000XX...
Page 558 APPENDIX A I/O Maps Table A-1 I/O Map (5 / 5) Address Register Abbreviation Access Peripheral Initial value 0000A2 Reserved 0000A7 0000A8 Watch-dog Control WDTC Watch-dog Timer XXXXX111 0000A9 Timebase Timer Control TBTC Timebase Timer 1XX00100 0000AA Reserved 0000AD 0000AE Flash Control Status FMCS Flash Memory...
Page 559 APPENDIX A I/O Maps ■ I/O Map (003XXX Addresses) Table A-2 I/O Map (003XXX Addresses) (1 / 5) Address Register Abbreviation Access Peripheral Initial value 003500 Reload L PRLL0 16-bit Programable XXXXXXXX Pulse Generator 0/1 003501 Reload H PRLH0 XXXXXXXX 003502 Reload L PRLL1...
Page 560 APPENDIX A I/O Maps Table A-2 I/O Map (003XXX Addresses) (2 / 5) Address Register Abbreviation Access Peripheral Initial value 003518 Serial Mode Register SMR3 UART3 00000000 003519 Serial Control Register SCR3 00000000 00351A Reception/Transmission Data RDR3/TDR3 00000000 Register 00351B Serial Status Register SSR3 00001000...
Page 561 APPENDIX A I/O Maps Table A-2 I/O Map (003XXX Addresses) (3 / 5) Address Register Abbreviation Access Peripheral Initial value 003530 Output Compare 0 OCCP0 Output Compare 0/1 XXXXXXXX 003531 Output Compare 0 OCCP0 XXXXXXXX 003532 Output Compare 1 OCCP1 XXXXXXXX 003533 Output Compare 1...
Page 562 APPENDIX A I/O Maps Table A-2 I/O Map (003XXX Addresses) (4 / 5) Address Register Abbreviation Access Peripheral Initial value 0035A0 IBSR 00000000 C bus status register C Interface 0035A1 IBCR 00000000 C bus control register 0035A2 ITBAL 00000000 C ten bit slave address register 0035A3 ITBAH...
Page 563 APPENDIX A I/O Maps Table A-2 I/O Map (003XXX Addresses) (5 / 5) Address Register Abbreviation Access Peripheral Initial value 0035E2 ROM Correction Address 0 PADR0 XXXXXXXX 0035E3 ROM Correction Address 1 PADR1 XXXXXXXX 0035E4 ROM Correction Address 1 PADR1 XXXXXXXX 0035E5 ROM Correction Address 1...
Page 564: Appendix B Instructions
APPENDIX B Instructions APPENDIX B Instructions Appendix B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective Address Field B.7 How to Read the Instruction List B.8 F MC-16LX Instruction List B.9 Instruction Map...
Page 565: Instruction Types
APPENDIX B Instructions Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 566: Addressing
APPENDIX B Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 567 APPENDIX B Instructions ■ Effective address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order None from the left.
Page 568: Direct Addressing
APPENDIX B Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution 2 2 3 3 4 4 5 5...
Page 569 APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing (This instruction transfers the eight low-order bits of A to the general-purpose MOV R0, A register R0.) Before execution 0 7 1 6 2 5 3 4 Memory space After execution 0 7 1 6 2 5 6 4 Memory space ●...
Page 570 APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) (This instruction causes an unconditional branch by direct branch 24-bit JMPP 333B20H...
Page 571 APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bit8 to bit15 are specified by the direct page register (DPR). Address bit16 to bit23 are specified by the data bank register (DTB).
Page 572 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 573 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector...
Page 574: Indirect Addressing
APPENDIX B Instructions Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 575 APPENDIX B Instructions ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj.
Page 576 APPENDIX B Instructions Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.) Before execution 0 7 1 6 2 5 3 4 Memory space 4 5 5 6...
Page 577 APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 578 APPENDIX B Instructions Figure B.4-9 Example of Register List (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E Memory space Memory space 34FE 34FE...
Page 579 APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB).
Page 580 APPENDIX B Instructions ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) (This instruction causes an unconditional branch by register indirect addressing.) JMP @RW0 Before execution 3 C 2 0...
Page 581: Execution Cycle Count
APPENDIX B Instructions Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■...
Page 582 APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in Code Operand each addressing mode Execution cycle count in each addressing mode...
Page 583 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address...
Page 584: Effective Address Field
APPENDIX B Instructions Effective Address Field Table B.6-1 shows the effective address field. ■ Effective address Field Table B.6-1 Effective address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order from the left.
Page 585: How To Read The Instruction List
APPENDIX B Instructions How to Read the Instruction List Table B.7-1 describes the items used in the F MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1 / 2) Item Description...
Page 586 APPENDIX B Instructions Table B.7-1 Description of Items in the Instruction List (2 / 2) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution.
Page 587 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (2 / 2) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing addr16 Direct addressing...
Page 588: F 2 Mc-16Lx Instruction List
APPENDIX B Instructions MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) MOV A,dir byte (A) ← (addr16) MOV A,addr16 byte (A) ←...
Page 589 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Byte) Mnemonic Operation word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi) MOVW A,RWi word (A) ← (ear) MOVW A,ear word (A) ←...
Page 590 APPENDIX B Instructions Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ← (A) + (eam) A,eam 4 + (a) byte (ear) ←...
Page 591 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 byte (eam) ← (eam) + 1 5+(a) 2 x (b) byte (ear) ← (ear) - 1 byte (eam) ← (eam) - 1 5+(a) 2 x (b) word (ear) ←...
Page 592 APPENDIX B Instructions Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) DIVU A,eam word (A) / byte (eam)
Page 593 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) A,eam word (A) / byte (eam) quotient →...
Page 594 APPENDIX B Instructions Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam) A,eam 4+(a) byte (ear) ← (ear) and (A) ear,A byte (eam) ←...
Page 595 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ← (A) or (eam) A,eam 7+(a) long (A) ←...
Page 596 APPENDIX B Instructions Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← With right rotation carry RORC byte (A) ← With left rotation carry ROLC byte (ear) ← With right rotation carry RORC byte (eam) ← With right rotation carry RORC 5+(a) 2 x (b)
Page 597 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/BNE Branch on (Z) = 0 BC/BLO Branch on (C) = 1 BNC/BHS Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0...
Page 598 APPENDIX B Instructions Table B.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9 Branch on byte (eam) not equal to imm8...
Page 599 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (PS) PUSHW (SP) ←...
Page 600 APPENDIX B Instructions Table B.8-16 21 Bit Operand Instructions Mnemonic Operation byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp bit (dir:bp)b ← (A) MOVB dir:bp,A 2 x (b) bit (addr16:bp)b ← (A) MOVB addr16:bp,A 2 x (b)
Page 601 APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic Operation byte transfer @AH+ ← @AL+, counter = RW0 MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter RW0 SCEQ / SCEQI byte search @AH- ←...
Page 602: Instruction Map
APPENDIX B Instructions Instruction Map Each F MC-16LX instruction code consists of 1 byte or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1...
Page 603 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction..Byte 1 Instruction code Byte 2 Operand Operand [Basic page map] [Extended page map] (*1) *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 604 APPENDIX B Instructions Table B.9-2 Basic Page Map...
Page 605 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6C...
Page 606 APPENDIX B Instructions Table B.9-4 Character String Operation Instruction Map (First Byte = 6E...
Page 607 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6F...
Page 608 APPENDIX B Instructions Table B.9-6 ea Instruction 1 (First Byte = 70...
Page 609 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71...
Page 610 APPENDIX B Instructions Table B.9-8 ea Instruction 3 (First Byte = 72...
Page 611 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73...
Page 612 APPENDIX B Instructions Table B.9-10 ea Instruction 5 (First Byte = 74...
Page 613 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75...
Page 614 APPENDIX B Instructions Table B.9-12 ea Instruction 7 (First Byte = 76...
Page 615 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77...
Page 616 APPENDIX B Instructions Table B.9-14 ea Instruction 9 (First Byte = 78...
Page 617 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79...
Page 618 APPENDIX B Instructions Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A...
Page 619 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B...
Page 620 APPENDIX B Instructions Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C...
Page 621 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D...
Page 622 APPENDIX B Instructions Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E...
Page 623 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F...
Page 624: Appendix C Timing Diagrams In Flash Memory Mode
APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90945 series during Flash Memory mode is shown below. ■ Data Read by Read Access Figure C-1 Timing Diagram for Read Access Address stable AQ16 to AQ0...
Page 625 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (WE Control) Figure C-2 Write, Data Polling, Read (WE Control) Third bus cycle Data polling AQ18 7AAAA GHWL WHWH1 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data : Output of write data Note:...
Page 626 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (CE Control) Figure C-3 Timing Diagram for Write Access (CE Control) Third bus cycle Data polling 7AAAA AQ18 to AQ0 GHWL WHWH1 DQ7 to DQ0 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data...
Page 627 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Chip Erase/Sector Erase Command Sequence Figure C-4 Timing Diagram for Write Access (Chip Erasing/Sector Erasing) AQ18 7AAAA 75555 7AAAA 7AAAA 75555 GHWL Note: SA is the sector address at sector erasing. 7AAAA (or 6AAAA ) is the address at chip erasing.
Page 628 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Data Polling Figure C-5 Timing Diagram for Data Polling High impedance DQ7 = Valid data WHWH1 WHWH2 DQ6 to DQ0 DQ6 to DQ0 DQ6 to DQ0 = Invalid = Valid data * DQ7 is valid data (The device terminates automatic operation).
Page 629 APPENDIX C Timing Diagrams in Flash Memory Mode ■ RY/BY Timing during Writing/Erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/Erasing Rising edge of last write pulse Writing or erasing RY/BY BUSY ■ RST and RY/BY Timing Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset RY/BY Ready...
Page 630 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Enable Sector Protect/Verify Sector Protect Figure C-9 Enable Sector Protect/Verify Sector Protect AQ18 to AQ9 AQ8, AQ2, and AQ1 (AQ8, AQ2, AQ1) = (0, 1, 0) 12 V 12 V VLHT VLHT OESP DQ7 to DQ0...
Page 631 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation 12 V Write/erase command sequence VLHT RY/BY...
Page 632: Appendix D List Of Interrupt Vectors
APPENDIX D List of Interrupt Vectors APPENDIX D List of Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00 to FFFFFF in the memory area and also used for software interrupts. ■ List of Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90945 series.
Page 633 APPENDIX D List of Interrupt Vectors Table D-1 Interrupt Vectors (2 / 2) Software Vector Vector Vector Mode Interrupt interrupt Hardware interrupt address L address M address H register instruction FFFF9C FFFF9D FFFF9E INT 24 Unused FFFF98 FFFF99 FFFF9A INT 25 Unused Input capture 0/1 FFFF94...
Page 634 APPENDIX D List of Interrupt Vectors ■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90945 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1 / 2) Interrupt vector Interrupt control register Interrupt cause...
Page 635 APPENDIX D List of Interrupt Vectors Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2 / 2) Interrupt vector Interrupt control register Interrupt cause clear Number Address Number Address FFFF78 Serial I/O 0000BB ICR11 FFFF74 FFFF70 UART 0 RX 0000BC ICR12 FFFF6C...
Page 636 APPENDIX D List of Interrupt Vectors...
Page 637: Index
INDEX The index follows on the next page. This is listed in alphabetic order.
Page 638 Index Numerics 1M-bit Flash Memory Sector Configuration of the 1M-bit 16-bit Free-running Timer Flash Memory ........488 16-bit Free Run Timer Timing......180 24-bit Operand 16-bit Free Run Timer Operation ....... 179 24-bit Operand Specification....... 30 16-bit Free-running Timer......... 170 2M-bit Flash Memory 16-bit Free-running Timer 0 and 1 .....
Page 639 Bank Addressing Types........31 Direct Addressing ..........552 Indirect Addressing...........558 Accumulator (A)..........36 ADER A/D Control Status Register Lower Bits of the Analog Input Enable Register A/D Control Status Register 0 (ADCS0) .... 256 (ADER0) ..........253 Upper Bits of the A/D Control Status Register Upper Bits of the Analog Input Enable/ (ADCS1)..........
Page 640 Baud Rate Generator Register Bus Operation Stop Bit Configuration of Baud Rate Generator Register Conditions for Canceling Bus Operation Stop (BGR02/03 and BGR12/13) ....328 (HALT=0).......... 426 Conditions for Setting Bus Operation Stop (HALT=1).......... 426 Bit Configuration of Baud Rate Generator Register State During Bus Operation Stop (HALT=1) ..
Page 641 Clock CMOD Block Diagram of the Clock Generation Block Sample Output Waveform when CMOD0 and ............82 " ........187 CMOD1= "00 Clock Mode Transition ........90 Sample Output Waveform when CMOD0 and Clock Modulator..........91 CMOD1= "10 " ........190 Clock Prescaler Settings ........385 Sample Output Waveform when CMOD0 and Clock Selection Registers ........
Page 642 Control Status Register (CSR) (Upper) ....423 Data Format Transfer Data Format ........293 Control Status Register (CSR-lower) Contents ..........422 Data Frame Control Status Register (CSR-upper) Processing for Reception of Data Frame and Remote Contents ..........424 Frame ..........457 Control Status Register of Free-running Timer Data Polling (Lower) ..........
Page 643 DLCRx ELVR DLC Register x (x=0 to 15) (DLCRx) ....451 Request Level Setting Register (ELVR: External Level Register) ........238 Data Polling Flag (DQ7)........499 ENIR Sector Erase Timer Flag (DQ3) ......503 Interrupt/DTP Enable Register (ENIR: Interrupt Timing Limit Exceeded Flag (DQ5)....502 Request Enable Register)......237 Toggle Bit Flag (DQ6) ........
Page 644 External Interrupt Detailed Explanation of Flash Memory Write/Erase External Interrupt Operation ......239 ............507 Switching between DTP and External Interrupt Erasing All Data in the Flash Memory (Erasing Chips) Requests..........241 ............511 Erasing Optional Data (Erasing Sectors) in the Flash External Interrupt Request Register Memory ..........
Page 645 IBSR Control Status Register of Free-running Timer (Upper) ..........178 Bus Status Register (IBSR)........370 Data Register of Free-running Timer....175 Bus Status Register (IBSR) Contents ....371 ICCR Clock Control Register (ICCR) ......383 Clock Control Register (ICCR) Contents ....384 General-purpose Registers General-purpose Registers ........
Page 646 Instruction Map Switching to a Standby Mode and Interrupt ..136 Structure of Instruction Map......586 Transmission Interrupt Generation and Flag Set Timing ..........334 Instructions Transmission Interrupt Request Generation Interrupt Disable Instructions ......46 Timing..........335 Precautions for Use of "DIV A, Ri" and "DIVW A, OS ......
Page 647 MB90F946A Block Diagram of MB90F946A ......6 Last Event Indicator Register Pin Assignment of MB90F946A ......10 Last Event Indicator Register (LEIR) ....427 MB90F947 Last Event Indicator Register (LEIR) Basic Configuration of MB90F947 Serial Contents..........428 Programming Connection .....524 LEIR Block Diagram of MB90F947(A)/ Last Event Indicator Register (LEIR) ....
Page 648 Example of Minimum Connection to the Flash Sample Program for Single Conversion Mode OS........267 Microcomputer Programmer (User Power Using EI Supply Used) ........532 Mode Data Mode Status of Pins after Mode Data is Read....114 Alternative Mode ..........491 Bus Mode Setting Bits ........
Page 649 Oscillation Stabilization Wait Time PADR Oscillation Stabilization Wait Time ..... 93, 137 Program Address Detection Registers (PADR0 to PADR2) ......473 Reset Causes and Oscillation Stabilization Wait Times ............106 Parity Oscillator Parity Bit ............294 Connection of an Oscillator or an External Clock to the Microcontroller......
Page 650 PPG1 Operation Mode Control Register PSCCR PPG1 Operation Mode Control Register (PPGC1) Configuration of the PLL and Special Configuration ............222 Control Register (PSCCR) ..... 88 PPGC Pulse Width PPG0 Operation Mode Control Register (PPGC0) Relationship between 8/16-bit PPG Reload Value and ............
Page 651 Reception Interrupt Reset Causes and Oscillation Stabilization Wait Times ............106 Reception Interrupt Generation and Flag Set Timing ............333 Setting the Flash Memory to the Read/Reset State ............508 Reception Interrupt Enable Register Status of Pins During a Reset ......114 Reception Interrupt Enable Register (RIER) ............
Page 652 Sample Output Waveform when CMOD0 and Serial Mode Control Register (UMC0) Contents " ........190 ............282 CMOD1= "10 Sample Output Waveform when CMOD0 and Serial Mode Control Status Register CMOD1= "11 " ........191 Bit Functions of Serial Mode Control Status Register Sample Output Waveform with Two Compare (SMCS) ..........
Page 653 Sleep Mode Release of Sleep Mode ........128 Priorities of the STP, SLP, and TMD Bits ...123 Switching to Sleep Mode ........127 Structure Structure ............67 Priorities of the STP, SLP, and TMD Bits ..123 Switching ..............137 SMCS Synchronization Bit Functions of Serial Mode Control Status Register Synchronization Methods ........344 (SMCS)..........
Page 654 Timer Control Register Transmission Interrupt Enable Register Register Contents of Timer Control Register Transmission Interrupt Enable Register (TIER) (TMCSR0) ......... 204 ............439 Timer Control Register (TMCSR0) ....204 Transmission Request Register Timer Register Transmission Request Register (TREQR)... 434 Register Layout of 16-bit Timer Register (TMR0)/ Transmission RTR Register 16-bit Reload Register (TMRLR0) Transmission RTR Register (TRTRR) ....
Page 655 User Power Supply Watch-dog Timer Watch-dog Timer Block Diagram ......162 Example of Serial Programming Connection (User Power Supply Used) ....528 Watch-dog timer behavior at reset .......167 User Stack Pointer Watch-dog timer behavior in stop mode etc..166 User Stack Pointer (USP) and System Stack Pointer Watch-dog Timer Control Register (SSP) ...........
Page 657 CM44-10134-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90945 Series HARDWARE MANUAL February 2006 the first edition FUJITSU LIMITED Electronic Devices Published Business Promotion Dept. Edited...