Input-Data Register (Sidr0/1) And Output-Data Register (Sodr0/1); Fig. 12.7 Input Data Register (Sidr0/1); Fig. 12.8 Output Data Register (Sodr0/1) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
12.4.4 Input Data Register (SIDR0/1) and Output Data Register (SODR0/1)
The input data register (SIDR0/1) is the receive register for serial data; the output data register (SODR0/1) is
the transmit register for serial data. The SIDR0/1 and the SODR0/1 registers are placed at the same
address.
n Input data register (SIDR0/1)
Figure 12.7 shows the bit configuration of input data register.
Address bit 7
CH0: 000036
H
CH1: 00003A
H
R: Read-only
X: Undefined
The input data register stores the received data. The serial-data signal transmitted to the SIN0 pin is
converted via the shift register and then stored in this register. When the data length is 7 bits, the upper 1 bit
(D7) is invalid data. When receive data is stored in this register, the receive data full flag bit (SSR: RDRF) is
set to 1. When the receive interrupt request is already enabled at this point, a receive interrupt is generated.
Read SIDR0/1 when the RDRF of the status register (SSR0/1) is 1. The RDRF is automatically cleared to 0
when SIDR0/1 is read. At a receive error (SSR: PE, ORE, or FRE), the SIDR0/1 data is invalidated.
n Output data register (SODR0, SODR1)
Figure 12.8 shows the bit configuration of output data register.
Address
CH0: 000036
H
CH1: 00003A
H
W: Write-only
X: Undefined
When transmit data is written to this register when transmission is enabled, transmit data is transferred to the
transmission shift register, converted to serial data, and output from the serial-data output pin (SOT0 pin).
When the data length is 7 bits, the upper 1 bit (D7) is invalid data.
When transmit data is written to this register, the transmit data empty flag (SSR: TDRE) is cleared to 0; and
when transfer to the transmit shift register is completed, that flag is set to 1. When the TDRE bit is 1, the
next send data can be written. When output of the transmit interrupt request is already enabled at this point,
a transmit interrupt is generated. Write the next transmit data when a transmit interrupt is generated or the
TDRE bit is 1.
Note: SODR0/1 is a write-only register and SIDR0/1 is a read-only register. However, since they are
placed at the same address, the write and read values are different. Consequently, do not use
instructions that perform read-modify-write (RMW) operation such as INC and DEC instructions.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
bit 6 bit 5
D7 D6 D5
R R R

Fig. 12.7 Input Data Register (SIDR0/1)

bit 7 bit 6 bit 5
D7 D6 D5
W W W

Fig. 12.8 Output Data Register (SODR0/1)

bit 4 bit 3 bit 2
D4 D3 D2
R R R
bit 4 bit 3 bit 2
D4 D3 D2
W W W
12-16
bit 1 bit 0
D1 D0 Initial value
R R XXXXXXXX
bit 1 bit 0
D1 D0
Initial value
W W XXXXXXXX
B
B