Serial Input Data Register (Sidr) And Serial Output Data Register (Sodr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 17 UART
17.3.3 Serial Input Data Register (SIDR) and Serial Output Data
Register (SODR)
The serial input data register (SIDR) and serial output data register (SODR) are receiver
and transmitter data buffer registers.
■ Configuration of Serial Input Data Register (SIDR) and Serial Output Data Register (SODR)
If SIDR or SODR data is 7 bits long, the high-order 1 bit (D7) becomes invalid. Write data into
the SODR register when the TDRE of the SSR register is "1".
Figure 17.3-4 Configuration of Serial Input Data Register (SIDR) and Serial Output Data Register (SODR)
Serial input register/
serial output register
Address:000022
H
Read/write
Initial value
Note:
Writing data at this address means writing data into the SODR register; reading data at this
address means reading data from the SIDR register.
266
bit 7 6 5
D7 D6 D5 D4
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X)
4 3 2 1
D3 D2 D1
(X) (X) (X)
0
D0 SIDR(read)
SODR(write)
(X)