Clock Select Register (Ckscr); Fig. 4.3 Configuration Of Clock Select Register (Ckscr) - Fujitsu MB90420/5 (A) Series Hardware Manual

4.3 Clock Select Register (CKSCR)

The clock select register (CKSCR) switches between the main clock and the PLL clock, selects the
oscillation stabilization wait time and the PLL clock multiplication rate.
n Configuration of clock select register (CKSCR)
Figure 4.3 shows the configuration of the clock select register (CKSCR), and Table 4-1 explains the function
of each bit of the register.
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
0000A1
SCM MCM WS1 WS0 SCS MCS CS1 CS0
H
R/W
HCLK : Oscillation clock
R/W : Both read and write
R : Read only

: Not used
: Initial value
Note: The machine clock select bit is initialized to 1 (indicating that the main clock is selected) at a reset.
R R/W R/W R/W
CS1
0
0
1
1
MCS
0
1
SCS
0
1
WS1
0
0
1
1
18
*: 2 /HCLK (about 65.54 ms) is used at power-on reset.
MCM
0
1
SCM
0
1

Fig. 4.3 Configuration of Clock Select Register (CKSCR)

CLOCK
bit 9 bit 8 bit 7
(LPMCR)
R/W R/W R/W
Multiplication Rate Select Bits
The parenthesized values are the values when
CS0
the oscillation clock is 4 MHz.
1 × HCLK (4 MHz)
0
2 × HCLK (8 MHz)
1
3 × HCLK (12 MHz)
0
4 × HCLK (16 MHz)
1
Machine Clock Select Bit
The PLL clock is selected.
The main clock is selected.
Machine Clock Select Bit (Sub)
The sub-clock is selected.
The main clock is selected.
Oscillation Stabilization Wait Time Select Bits
WS0 The parenthesized values are the values when
the oscillation clock frequency is 4 MHz.
/HCLK (about 256 µs)
10
0 2
13
1 2 /HCLK (about 2.05 ms)
15
0 2 /HCLK (about 8.19 ms)
17
1 2 /HCLK (about 32.77 ms)
Machine Clock Display Bit
During operation on the PLL clock.
During operation on the main clock.
Machine Clock Display Bit (Sub)
During operation on the sub-clock.
During operation on the main clock.
4-7
Initial value
bit 0
11111100
B
*