Clock Selection Register (Ckscr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 5 CLOCK
5.3

Clock Selection Register (CKSCR)

The clock selection register (CKSCR) is used to set switching between the main clock
and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a
PLL clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-1 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-1 Configuration of the Clock Selection Register (CKSCR)
bit 15
Address
0000A1 RESV MCM WS1
H
R/W
HCLK: Oscillation clock frequency
R/W: Read/write
R: Read only
- : Unused
: Initial value
Note:
If the machine clock selection bit is not set, the main clock is used as the machine clock.
82
14 13 12 11
WS0 RESV MCS
R R/W R/W R/W R/W
* At power-on reset, the oscillation stabilization wait interval is 2
10 9 8 7
CS0
CS1 (LPMCR)
R/W R/W
Multiplier selection bits
CS1 CS0
The resulting clock frequency is shown in parentheses
0 0 1 x HCLK (4MHz)
0 1 2 x HCLK (8MHz)
1 0 3 x HCLK (12MHz)
1 1 4 x HCLK (16MHz)
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
Oscillation stabilization wait interval selection bits
WS1 WS0
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
10
0 0
/ HCLK (Approx. 0.256ms)
2
13
0 1
2 / HCLK (Approx. 2.05ms)
15
1 0
2 / HCLK (Approx. 8.19ms)
17
1 1
2 / HCLK (Approx. 32.74ms)*
MCM Machine clock indication bit
0 A PLL clock is used as the machine clock.
1 The main clock is used as the machine clock.
Reserved bit
RESV
1 must always be written to these bits.
0
Initial value
11111100
B
18
/HCLK.