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9. Timers
TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and
TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower
8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the
CPU takes place via a temporary register (TEMP). For details see section 9.5.3, Interface with the
CPU.
Upon reset, TCFH and TCFL are each initialized to H'00.
• 16-bit mode (TCF)
16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The
TCF input clock is selected by TCRF bits CKSL2 to CKSL0.
TCFH can be cleared by a compare match signal. This designation is made in bit CCLRH in
TCSRF.
When TCF overflows from H'FFFF to H'0000, the overflow flag (OVFH) in TCSRF is set to 1.
If bit OVIEH in TCSRF is set to 1 when an overflow occurs, bit IRRTFH in interrupt request
register 2 (IRR2) will be set to 1; and if bit IENTFH in interrupt enable register 2 (IENR2) is
set to 1, a CPU interrupt will be requested.
• 8-bit mode (TCFH, TCFL)
When bit CKSH2 in timer control register F (TCRF) is set to 1, timer F functions as two
separate 8-bit counters, TCFH and TCFL. The TCFH (TCFL) input clock is selected by TCRF
bits CKSH2 to CKSH0 (CKSL2 to CKSL0).
TCFH (TCFL) can be cleared by a compare match signal. This designation is made in bit
CCLRH (CCLRL) in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, the overflow flag OVFH (OVFL) in
TCSRF is set to 1. If bit OVIEH (OVIEL) in TCSRF is set to 1 when an overflow occurs, bit
IRRTFH (IRRTHL) in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH
(IENTFL) in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested.
Rev.3.00 Jul. 19, 2007 page 230 of 532
REJ09B0397-0300
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