Renesas F-ZTAT H8 Series Hardware Manual page 300

10. Serial Communication Interface
Bit Rate Register (BRR)
Bit
BRR7
Initial value
Read/Write R/W
The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock
selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit
rate.
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Table 10.6 gives examples of how BRR is set in asynchronous mode. The values in
table 10.6 are for active (high-speed) mode.
Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode
Bit Rate
(bits/s) n N
110 1 70
150 0 207
300 0 103
600 0 51
1200 0 25
2400 0 12
⎯ ⎯
4800
⎯ ⎯
9600
⎯ ⎯
19200
31250 0 0
⎯ ⎯
38400
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7 6 5
BRR6 BRR5
1 1 1
R/W R/W
2 2.4576
Error
(%) n N
+0.03 1 86
+0.16 0 255
+0.16 0 127
+0.16 0 63
+0.16 0 31
+0.16 0 15
⎯
0 7
⎯
0 3
⎯
0 1
⎯ ⎯
0
⎯
0 0
4 3
BRR4 BRR3
1 1
R/W R/W
OSC (MHz)
4
Error
(%) n N
+0.31 1 141
0 1 103
0 0 207
0 0 103
0 0 51
0 0 25
0 0 12
⎯ ⎯
0
⎯ ⎯
0
⎯
0 1
⎯ ⎯
0
2 1
BRR2 BRR1 BRR0
1 1
R/W R/W
4.194304
Error
(%) n N
+0.03 1 148
+0.16 1 108
+0.16 0 217
+0.16 0 108
+0.16 0 54
+0.16 0 26
+0.16 0 13
⎯
0 6
⎯ ⎯ ⎯
⎯ ⎯
0
⎯ ⎯ ⎯
0
1
R/W
Error
(%)
−0.04
+0.21
+0.21
+0.21
−0.70
+1.14
−2.48
−2.48
⎯
⎯
⎯