Renesas F-ZTAT H8 Series Hardware Manual page 103

Bit 7—Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt
requests.
Bit 7: IENTA Description
0 Disables timer A interrupts
1 Enables timer A interrupts
Bit 6—SCI1 Interrupt Enable (IENS1): Bit 6 is used in the H8/3857 Group to enable or disable
SCI1 transfer complete interrupt requests. In the H8/3854 Group, this bit must always be cleared
to 0.
Bit 6: IENS1 Description
0 Disables SCI1 interrupts
1 Enables SCI1 interrupts
Bit 5—Wakeup Interrupt Enable (IENWP): Bit 5 enables or disables WKP
requests.
Bit 5: IENWP Description
Disables interrupt requests from WKP
0
Enables interrupt requests from WKP
1
Bits 4, 3, 1, and 0—IRQ
IEN0): Bits 4 to 0 enable or disable IRQ
Bit n: IENn Description
Disables interrupt request IRQn
0
Enables interrupt request IRQn
1
Note: n = 4, 3, 1, or 0
Bit 2—IRQ Interrupt Enable (IEN2): Bit 2 is used in the H8/3857 Group to enable or disable
2
IRQ
interrupt requests. In the H8/3854 Group, this bit must always be cleared to 0.
2
Bit 2: IEN2 Description
Disables interrupt request IRQ
0
Enables interrupt request IRQ
1
, IRQ , IRQ , and IRQ
4 3 1
, IRQ
4
to WKP
7 0
to WKP
7 0
Interrupt Enable (IEN4, IEN3, IEN1,
0
, IRQ , and IRQ
interrupt requests.
3 1 0
2
2
Rev.3.00 Jul. 19, 2007 page 77 of 532
3. Exception Handling
(initial value)
(initial value)
to WKP interrupt
7 0
(initial value)
(initial value)
(initial value)
REJ09B0397-0300