Renesas F-ZTAT H8 Series Hardware Manual page 302

8-bit single-chip microcomputer
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10. Serial Communication Interface
9.8304
Bit Rate
(bits/s)
n
N
110
2
86
150
1
255
300
1
127
600
0
255
1200
0
127
2400
0
63
4800
0
31
9600
0
15
19200
0
7
31250
0
4
38400
0
3
Notes: 1. Settings should be made so that error is within 1%.
2. BRR setting values are derived by the following equation.
OSC
N =
64 × 2
B:
Bit rate (bits/s)
BRR baud rate generator setting (0 ≤ N ≤ 255)
N:
OSC: Value of φ
n:
Baud rate generator input clock number (n = 0 to 3)
(The relation between n and the clock is shown in table 10.7.)
3. The error values in table 10.6 were derived by performing the following calculation and
rounding off to two decimal places.
Error (%) =
B: Bit rate found from n, N, and OSC
R: Bit rate listed in left column of table 10.6
Rev.3.00 Jul. 19, 2007 page 276 of 532
REJ09B0397-0300
OSC (MHz)
10
Error
(%)
n
N
+0.31
2
88
0
2
64
0
1
129
0
1
64
0
0
129
0
0
64
0
0
32
0
0
15
0
0
7
−1.70
0
4
0
0
3
× 10
6
– 1
× B
2n
(MHz)
OSC
B – R
× 100
R
Error
(%)
−0.25
+0.16
+0.16
+0.16
+0.16
+0.16
−1.36
+1.73
+1.73
0
+1.73

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