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3. Exception Handling
Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ
Bit 3—IRQ
3
Bit 3: IEG3
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Bit 2—IRQ
Edge Select (IEG2): Bit 2 is used in the H8/3857 Group to select the input sensing
2
of pin IRQ
/TMIC. In the H8/3854 Group, this bit must always be cleared to 0.
2
Bit 2: IEG2
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ
Bit 1—IRQ
1
Bit 1: IEG1
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ
Bit 0—IRQ
0
Bit 0: IEG0
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Interrupt Enable Register 1 (IENR1)
Bit
IENTA
Initial value
Read/Write
R/W
Note:
*
Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Rev.3.00 Jul. 19, 2007 page 76 of 532
REJ09B0397-0300
/TMIF pin input is detected
3
/TMIF pin input is detected
3
/TMIC pin input is detected
2
/TMIC pin input is detected
2
/TMIB pin input is detected
1
/TMIB pin input is detected
1
pin input is detected
0
pin input is detected
0
7
6
5
IENS1*
IENWP
0
0
0
R/W
R/W
4
3
IEN4
IEN3
IEN2*
0
0
R/W
R/W
R/W
/TMIF.
3
(initial value)
(initial value)
/TMIB.
1
(initial value)
.
0
(initial value)
2
1
0
IEN1
IEN0
0
0
0
R/W
R/W
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