Renesas F-ZTAT H8 Series Hardware Manual page 527

8-bit single-chip microcomputer
Hide thumbs Also See for F-ZTAT H8 Series:
Table of Contents

Advertisement

SYSCR2—System control register 2
Bit
Initial value
Read/Write
Medium speed on flag
0 Operates in active (high-speed) mode
1 Operates in active (medium-speed) mode
Direct transfer on flag
0 When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode.
1
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1.
Noise elimination sampling frequency select
0 Sampling rate is φ
1 Sampling rate is φ
Legend:
Don't care
*
7
6
5
1
1
1
/16
OSC
/4
OSC
Appendix B Internal I/O Registers
H'F1
4
3
NESEL
DTON
MSON
0
0
R/W
R/W
Subactive mode clock select
0
1
Rev.3.00 Jul. 19, 2007 page 501 of 532
System control
2
1
SA1
SA0
0
0
R/W
R/W
R/W
φ /8
0
W
φ /4
1
W
φ /2
*
W
REJ09B0397-0300
0
0

Advertisement

Table of Contents
loading

Table of Contents