Table of Contents
Advertisement
6. ROM
SYSCR3 is initialized to H'00 by a reset.
Bits 7 to 4—Reserved Bits: Bits 7 to 4 are reserved; they are always read as 0 and cannot be
modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Bit 3 controls CPU access to the
flash memory control registers (FLMCR1, FLMCR2, and EBR). When the FLSHE bit is set to 1,
the flash memory control registers can be read and written to. When FLSHE is cleared to 0, the
flash memory control registers are unselected. In this case, the contents of the flash memory
control registers are retained.
Bit 3: FLSHE Description
0
Flash memory control registers are unselected for addresses H'FF80 to H'FF83
1
Flash memory control registers are selected for addresses H'FF80 to H'FF83
Bits 2 to 0—Reserved Bits: Bits 2 to 0 are reserved; they are always read as 0 and cannot be
modified.
6.4
On-Board Programming Modes
When an on-board programming mode is selected, the on-chip flash memory can be programmed,
erased, and verified. There are two on-board programming modes: boot mode and user program
mode. Table 6.5 shows the pin settings for transition to each mode. A state transition diagram for
flash memory related modes is shown in figure 6.3.
Table 6.5
On-Board Programming Mode Selection
Mode
MCU Mode
Boot mode
User program mode*
Notes: 1. The FWE pin should normally be set to 0. Before performing programming, erasing, or
verifying, set the FWE pin to 1 and make a transition to user program mode.
2. For the high level application timing, see items (f) and (g) under (3) Notes on Use of
Boot Mode in section 6.4.1, Boot Mode.
Rev.3.00 Jul. 19, 2007 page 132 of 532
REJ09B0397-0300
1
FWE
TEST2
2
1*
0
1
1
(initial value)
Pins
TEST
0
0
Advertisement
Table of Contents
