Renesas F-ZTAT H8 Series Hardware Manual page 297

Bit 6—Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is
receive data in RDR.
Bit 6: RDRF Description
0 Indicates there is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF.
When data is read from RDR by an instruction.
1 Indicates that there is receive data in RDR
Setting condition:
When receiving ends normally, with receive data transferred from RSR to RDR
Note: If a receive error is detected at the end of receiving, or if bit RE in serial control register 3
(SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An
overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set
to 1. If this happens, receive data will be lost.
Bit 5—Overrun Error (OER): Bit 5 is a status flag indicating that an overrun error has occurred
during data receiving.
Bit 5: OER Description
0 Indicates that data receiving is in progress or has been completed
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
1 Indicates that an overrun error occurred in data receiving
Setting condition:
When data receiving is completed while RDRF is set to 1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and
keeps its previous state.
2. RDR keeps the data received prior to the overrun; data received after that is lost. While
OER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
10. Serial Communication Interface
2
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Rev.3.00 Jul. 19, 2007 page 271 of 532
(initial value)
1
(initial value)
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REJ09B0397-0300