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Bits 4 and 3—Reserved Bits: Bits 4 and 3 are reserved; they are always read as 1, and cannot be
modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0): Bits 2 to 0 select the clock input to TCC. For
external clock counting, either the rising or falling edge can be selected.
Bit 2: TMC2
Bit 1: TMC1
0
0
1
1
0
1
Note:
*
The edge of the external event signal is selected by bit IEG2 in the IRQ edge select
register (IEGR). See section 3.3.2, Interrupt Control Registers for details on the IRQ
edge select register. Be sure to set bit IRQ2 in port mode register 1 (PMR1) to 1 before
setting bits TMC2 to TMC0 to 111.
Timer Counter C (TCC)
Bit
TCC7
Initial value
Read/Write
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.
TCC is allocated to the same address as timer load register C (TLC).
Upon reset, TCC is initialized to H'00.
Bit 0: TMC0
0
1
0
1
0
1
0
1
7
6
5
TCC6
TCC5
0
0
0
R
R
R
Description
Internal clock: φ/8192
Internal clock: φ/2048
Internal clock: φ/512
Internal clock: φ/64
Internal clock: φ/16
Internal clock: φ/4
Internal clock: φ
/4
W
External event (TMIC): rising or falling edge*
4
3
TCC4
TCC3
TCC2
0
0
R
R
Rev.3.00 Jul. 19, 2007 page 223 of 532
9. Timers
(initial value)
2
1
0
TCC1
TCC0
0
0
0
R
R
R
REJ09B0397-0300
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