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Appendix B Internal I/O Registers
MDCR—Mode control register
Bit
:
7
⎯
Initial value
:
0
⎯
Read/Write
:
Note: * Determined by the TEST and TEST2 pins.
SYSCR3—System control register 3
Bit
:
7
⎯
Initial value
:
0
⎯
Read/Write
:
Rev.3.00 Jul. 19, 2007 page 472 of 532
REJ09B0397-0300
6
5
4
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
6
5
4
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Flash memory control register enable
0
Flash memory control registers are unselected
1
Flash memory control registers are selected
H'89
(On-chip flash memory version only)
3
2
⎯
⎯
0
0
⎯
⎯
H'8F
(On-chip flash memory version only)
3
2
⎯
FLSHE
0
0
⎯
R/W
Flash memory
1
0
TSDS2
TSDS1
⎯*
⎯*
R
R
Test pin monitor bits
Flash memory
1
0
⎯
⎯
0
0
⎯
⎯
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