Renesas F-ZTAT H8 Series Hardware Manual page 505

SCR3—Serial control register 3
Bit
TIE
Initial value
Read/Write
R/W
Clock enable
Bit 1
CKE1
Transmit end interrupt enable
0 Transmit end interrupt (TEI) disabled
1 Transmit end interrupt (TEI) enabled
Multiprocessor interrupt enable
0 Multiprocessor interrupt request disabled (ordinary receive operation)
[Clearing condition]
Multiprocessor bit receives a data value of 1
1 Multiprocessor interrupt request enabled
Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive
error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and
OER are not set.
Receive enable
0 Receive operation disabled (RXD is a general I/O port)
1 Receive operation enabled (RXD is the receive data pin)
Transmit enable
0 Transmit operation disabled (TXD is a general I/O port)
1 Transmit operation enabled (TXD is the transmit data pin)
Receive interrupt enable
0 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0 Transmit data empty interrupt request (TXI) disabled
1 Transmit data empty interrupt request (TXI) enabled
7 6 5
RIE TE
0 0 0
R/W R/W
Bit 0
CKE0 Communication Mode
0
0 Asynchronous
Synchronous
1
Asynchronous
Synchronous
0
1 Asynchronous
Synchronous
1
Asynchronous
Synchronous
Appendix B Internal I/O Registers
H'AA
4 3 2
RE MPIE TEIE
0 0 0
R/W R/W R/W
Description
Clock Source
Internal clock
Internal clock
Internal clock
Reserved (Do not set
this combination)
External clock
External clock
Reserved (Do not set
this combination)
Reserved (Do not set
this combination)
Rev.3.00 Jul. 19, 2007 page 479 of 532
SCI3
1 0
CKE1 CKE0
0 0
R/W R/W
SCK Pin Function
3
I/O port
Serial clock output
Clock output
Reserved (Do not set
this combination)
Clock input
Serial clock input
Reserved (Do not set
this combination)
Reserved (Do not set
this combination)
REJ09B0397-0300