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Appendix A CPU Instruction Set
Mnemonic
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @Rd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @Rd
BNOT Rn, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
Rev.3.00 Jul. 19, 2007 page 446 of 532
REJ09B0397-0300
Operation
B (#xx:3 of Rd8) ← 1
B (#xx:3 of @Rd16) ← 1
B (#xx:3 of @aa:8) ← 1
B (Rn8 of Rd8) ← 1
B (Rn8 of @Rd16) ← 1
B (Rn8 of @aa:8) ← 1
B (#xx:3 of Rd8) ← 0
B (#xx:3 of @Rd16) ← 0
B (#xx:3 of @aa:8) ← 0
B (Rn8 of Rd8) ← 0
B (Rn8 of @Rd16) ← 0
B (Rn8 of @aa:8) ← 0
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
B (#xx:3 of Rd8) → Z
B (#xx:3 of @Rd16) → Z
B (#xx:3 of @aa:8) → Z
B (Rn8 of Rd8) → Z
B (Rn8 of @Rd16) → Z
B (Rn8 of @aa:8) → Z
Addressing Mode/
Instruction Length (Bytes)
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
Condition Code
I H N Z V C
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯
⎯ ⎯ 2
⎯ ⎯ ⎯
⎯ ⎯ 6
⎯ ⎯ ⎯
⎯ ⎯ 6
⎯ ⎯ ⎯
⎯ ⎯ 2
⎯ ⎯ ⎯
⎯ ⎯ 6
⎯ ⎯ ⎯
⎯ ⎯ 6
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