External Interrupts - Renesas F-ZTAT H8 Series Hardware Manual

Wakeup Interrupt Request Register (IWPR)
Bit
IWPF7
Initial value
Read/Write R/W*
Note: Only a write of 0 for flag clearing is possible.
*
IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP
WKP
are set to wakeup input and a pin receives a falling edge input. The flags are not cleared
0
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bits 7 to 0—Wakeup Interrupt Request Flags (WKPF7 to WKPF0)
Bit n: IWPFn Description
0 Clearing condition:
When IWPFn = 1, it is cleared by writing 0 to IWPFn
1 Setting condition:
IWPFn is set when pin WKP
input is detected at the pin
Note: n = 7 to 0
3.3.3

External Interrupts

The H8/3857 Group has 13 external interrupt sources, WKP
H8/3854 Group has 12 external interrupt sources, WKP
Interrupts WKP to WKP
0
pins WKP to WKP . When these pins are designated as WKP
0 7
5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request
register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by
clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR
I bit to 1.
When an interrupt exception handling request is received for interrupts WKP
bit is set to 1. The vector number for interrupts WKP
assigned the same vector number, the interrupt source must be determined by the exception
handling routine.
7 6 5
IWPF6 IWPF5
0 0 0
R/W* R/W*
: Interrupts WKP
7
4 3
IWPF4 IWPF3
0 0
R/W* R/W*
is set to wakeup interrupt input, and a falling edge
n
to WKP
7
to WKP , IRQ
7 0
to WKP are requested by falling edge inputs at
0 7
to WKP
0
to WKP is 9. Since all eight interrupts are
0 7
Rev.3.00 Jul. 19, 2007 page 83 of 532
3. Exception Handling
2 1
IWPF2 IWPF1 IWPF0
0 0
R/W* R/W*
, and IRQ to IRQ . The
0 4 0
, IRQ , IRQ , and IRQ
4 3 1
pins in port mode register
7
to WKP , the CCR I
0 7
REJ09B0397-0300
0
0
R/W*
to
7
.
0