Table Of Contents - Renesas F-ZTAT H8 Series Hardware Manual

8-bit single-chip microcomputer
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Table of Contents

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1.1
Overview...........................................................................................................................
1.2
Internal Block Diagram.....................................................................................................
1.3
Pin Arrangement and Functions........................................................................................
1.3.1
Pin Arrangement ..................................................................................................
1.3.2
Pin Functions ....................................................................................................... 20
...................................................................................................................... 27
2.1
Overview........................................................................................................................... 27
2.1.1
Features................................................................................................................ 27
2.1.2
Address Space...................................................................................................... 28
2.1.3
Register Configuration......................................................................................... 28
2.2
Register Descriptions ........................................................................................................ 29
2.2.1
General Registers ................................................................................................. 29
2.2.2
Control Registers ................................................................................................. 29
2.2.3
Initial Register Values.......................................................................................... 31
2.3
Data Formats ..................................................................................................................... 31
2.3.1
Data Formats in General Registers ...................................................................... 32
2.3.2
Memory Data Formats ......................................................................................... 33
2.4
Addressing Modes............................................................................................................. 34
2.4.1
Addressing Modes ............................................................................................... 34
2.4.2
Effective Address Calculation ............................................................................. 36
2.5
Instruction Set ................................................................................................................... 40
2.5.1
Data Transfer Instructions.................................................................................... 42
2.5.2
Arithmetic Operations.......................................................................................... 44
2.5.3
Logic Operations.................................................................................................. 45
2.5.4
Shift Operations ................................................................................................... 45
2.5.5
Bit Manipulations................................................................................................. 47
2.5.6
Branching Instructions ......................................................................................... 51
2.5.7
System Control Instructions................................................................................. 53
2.5.8
Block Data Transfer Instruction........................................................................... 54
2.6
Basic Operational Timing ................................................................................................. 55
2.6.1
Access to On-Chip Memory (RAM, ROM)......................................................... 55
2.6.2
Access to On-Chip Peripheral Modules ............................................................... 56
2.7
CPU States ........................................................................................................................ 57
2.7.1
Overview.............................................................................................................. 57
2.7.2
Program Execution State...................................................................................... 59
Contents
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Rev.3.00 Jul. 19, 2007 page xv of xxiv
REJ09B0397-0300
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