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Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA.
Bit 3:
Bit 2:
TMA3
TMA2
0
0
1
1
0
1
Timer Counter A (TCA)
Bit
TCA7
Initial value
Read/Write
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Bit 1:
Bit 0:
TMA1
TMA0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
7
6
5
TCA6
TCA5
0
0
0
R
R
R
Description
Prescaler and Divider Ratio
or Overflow Period
PSS, φ/8192
(initial value)
PSS, φ/4096
PSS, φ/2048
PSS, φ/512
PSS, φ/256
PSS, φ/128
PSS, φ/32
PSS, φ/8
PSW, 1 s
PSW, 0.5 s
PSW, 0.25 s
PSW, 0.03125 s
PSW and TCA are reset
4
3
TCA4
TCA3
0
0
R
R
Rev.3.00 Jul. 19, 2007 page 213 of 532
9. Timers
Function
Interval timer
Clock time base
2
1
TCA2
TCA1
TCA0
0
0
R
R
REJ09B0397-0300
0
0
R
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