Table of Contents
Advertisement
TCSRW—Timer control/status register W
Bit
Initial value
Read/Write
Bit 4 write inhibit
0
1
Timer counter W write enable
0
Writing of data to TCW is disabled
1
Writing of data to TCW is enabled
Bit 6 write inhibit
0
Writing to bit 6 is enabled
1
Writing to bit 6 is disabled
Note: * Can be written to only when the write condition is satisfied.
:
7
6
B6WI
TCWE
B4WI TCSRWE B2WI
:
1
0
:
R
R/(W)*
Watchdog timer reset
0
1
Bit 0 write inhibit
0
Writing to bit 0 is enabled
1
Writing to bit 0 is disabled
Watchdog timer on
0
Watchdog timer operation is disabled
1
Watchdog timer operation is enabled
Bit 2 write inhibit
0
Writing to bit 2 is enabled
1
Writing to bit 2 is disabled
Timer control/status register W write enable
0
Writing to bits 2 and 0 is disabled
1
Writing to bits 2 and 0 is enabled
Writing to bit 4 is enabled
Writing to bit 4 is disabled
Appendix B Internal I/O Registers
H'90
(On-chip flash memory version only)
5
4
3
1
0
1
R
R/(W)*
R
[Clearing conditions]
• Reset by RES pin
• When 0 is written to WRST while writing 0 to
B0WI when TCSRWE = 1
[Setting condition]
When TCW overflows and an internal reset
signal is generated
Rev.3.00 Jul. 19, 2007 page 473 of 532
Flash memory
2
1
0
WDON
B0WI
WRST
0
1
0
R/(W)*
R
R/(W)*
REJ09B0397-0300
Advertisement
Table of Contents
