Table of Contents
Advertisement
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
Error protection is released only by a reset.
Figure 6.14 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P bit or E bit is set to 1 in FLMCR1.
2. FLMCR1, FLMCR2, and EBR can be written to. However, registers will be initialized
if a transition is made to software standby mode in the error protection state.
3. The read value is undefined.
4. Before exception handling stack and vector read operations are performed.
Program mode
Erase mode
RD VF PR ER FLER = 0
Error
occurrence
Error protect mode
RD VF PR ER FLER = 1
Legend:
RD
: Memory read possible
VF
: Verify-read possible
PR
: Programming possible
ER
: Erasing possible
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.
RES = 0
Standby mode
Standby mode release
RD
: Memory read not possible
VF
: Verify-read not possible
PR
: Programming not possible
ER
: Erasing not possible
INIT
: Register (FLMCR1, FLMCR2, EBR) initialization state
Figure 6.14 Flash Memory State Transitions
Reset
(hardware protection)
RD VF PR ER
FLER = 0
FLMCR1, FLMCR2,
and EBR initialized
RES = 0
Error protect mode
(standby mode)
RD VF PR ER INIT
FLER = 1
FLMCR1, FLMCR2 (except FLER bit),
and EBR initialized
Rev.3.00 Jul. 19, 2007 page 147 of 532
6. ROM
REJ09B0397-0300
Advertisement
Table of Contents
