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Appendix B Internal I/O Registers
TLC—Timer load register C
Bit
TLC7
Initial value
Read/Write
W
TCRF—Timer control register F
Bit
TOLH
Initial value
Read/Write
W
Toggle output level H
0 Low level
1 High level
Legend:
*
Don't care
Rev.3.00 Jul. 19, 2007 page 486 of 532
REJ09B0397-0300
7
6
5
TLC6
TLC5
0
0
0
W
W
7
6
5
CKSH2
CKSH1
0
0
0
W
W
Clock select L
0
1 0 0
Toggle output level L
0 Low level
1 High level
Clock select H
0
16-bit mode selected. TCFL overflow signals are counted.
* *
1 0 0
Internal clock:
1
Internal clock:
1 0
Internal clock:
1
Internal clock:
H'B5
4
3
TLC4
TLC3
0
0
W
W
Reload value
H'B6
4
3
CKSH0
TOLL
0
0
W
W
External event (TMIF): Rising or falling edge
* *
Internal clock:
1
Internal clock:
1 0
Internal clock:
1
Internal clock:
φ/32
φ/16
φ/4
φ/2
(H8/3857 Group only)
2
1
TLC2
TLC1
0
0
W
W
2
1
CKSL2
CKSL1
0
0
W
W
φ/32
φ/16
φ/4
φ/2
Timer C
0
TLC0
0
W
Timer F
0
CKSL0
0
W
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