Renesas F-ZTAT H8 Series Hardware Manual page 131

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
Bit 6: STS2 Bit 5: STS1
0 0
1
1 *
Legend: * Don't care
Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock (φ) or subclock (φ
the CPU operating clock when watch mode is cleared. The resulting operation mode depends on
the combination of other control bits and interrupt input.
Bit 3: LSON Description
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ
Bits 2 to 0—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
System Control Register 2 (SYSCR2)
Bit
Initial value
Read/Write
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
Bit 4: STS0
0
1
0
1
*
7 6 5
⎯ ⎯ ⎯
1 1 1
⎯ ⎯ ⎯
Description
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
)
SUB
4 3
NESEL DTON
0 0
R/W R/W
Rev.3.00 Jul. 19, 2007 page 105 of 532
5. Power-Down Modes
(initial value)
SUB
(initial value)
2 1
MSON SA1
0 0
R/W R/W
REJ09B0397-0300
) as
0
SA0
0
R/W