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14. Dot Matrix LCD Controller (H8/3854 Group)
valid display data area. When INC is 1 and the value in XA2 to XA0 is H'4, the address is
incremented after the access specified by RMW.
14.2.5
Frame Frequency Setting Register (LR3)
Bit
7
⎯
⎯
Initial value
⎯
Read/Write
LR3 is an 8-bit write-only register that sets the frame frequency.
Upon reset, LR3 is initialized to H'00.
Bits 7 to 3—Reserved Bits: Bits 7 to 3 are reserved; they should always be cleared to 0.
Bits 2 to 0—Frame Frequency Setting (FS2 to FS0): Bits 2 to 0 control the subclock division
ratio and set the LCD frame frequency. The relationship between the LCD frame frequency f F
(Hz), the subclock frequency f W (Hz), the division ratio r, and the LCD duty 1/N is as follows:
Set a division ratio suitable for the characteristics of the LCD panel used. The correspondence
between register settings, division ratios, and frame frequencies at each display duty is shown in
table 14.3.
Rev.3.00 Jul. 19, 2007 page 382 of 532
REJ09B0397-0300
6
5
⎯
⎯
⎯
⎯
⎯
⎯
f
=
F
4
3
⎯
⎯
FS2
⎯
⎯
⎯
⎯
f
W
r
×
N
2
1
FS1
FS0
0
0
W
W
0
0
W
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