Renesas F-ZTAT H8 Series Hardware Manual page 474

Appendix A CPU Instruction Set
Mnemonic
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
JMP @Rn
JMP @aa:16
JMP @@aa:8
BSR d:8
JSR @Rn
JSR @aa:16
Rev.3.00 Jul. 19, 2007 page 448 of 532
REJ09B0397-0300
Operation Branching
Condition
B C⊕(#xx:3 of @Rd16) → C
B C⊕(#xx:3 of @aa:8) → C
⎯ PC ← PC+d:8
⎯ PC ← PC+2
⎯ If C ∨ Z = 0
⎯ condition C ∨ Z = 1
⎯ is true
C = 0
⎯ then
C = 1
⎯ PC ←
Z = 0
⎯ PC+d:8
Z = 1
⎯ else next;
V = 0
⎯
V = 1
⎯
N = 0
⎯
N = 1
⎯
N⊕V = 0
⎯
N⊕V = 1
⎯ Z ∨ (N⊕V) = 0
⎯ Z ∨ (N⊕V) = 1
⎯ PC ← Rn16
⎯ PC ← aa:16
⎯ PC ← @aa:8
⎯ SP–2 → SP
PC → @SP
PC ← PC+d:8
⎯ SP–2 → SP
PC → @SP
PC ← Rn16
⎯ SP–2 → SP
PC → @SP
PC ← aa:16
Addressing Mode/
Instruction Length (Bytes)
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
2
4
Condition Code
I H N Z V C
⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8