Operation - Renesas F-ZTAT H8 Series Hardware Manual

8-bit single-chip microcomputer
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10. Serial Communication Interface
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI
, which is shifted in the direction from the most
1
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is not fixed.
Serial Data Register L (SDRL)
Bit
7
6
5
4
3
2
1
0
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL is output from pin SO
starting from the least significant bit
1
(LSB). This data is than replaced by LSB-first data input at pin SI
, which is shifted in the
1
direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU.
SDRL must be written or read only after data transmission or reception is complete. If this register
is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL value upon reset is not fixed.
10.2.3

Operation

Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external
serial clock. Overrun errors can be detected when an external clock is used.
Clock
The serial clock can be selected from a choice of eight internal clocks and an external clock. When
an internal clock source is selected, pin SCK
becomes the clock output pin. When continuous
1
clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (φ/1024
Rev.3.00 Jul. 19, 2007 page 256 of 532
REJ09B0397-0300

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