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Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare
match and overflow interrupt requests.
Bit 2: IENTFL
Description
0
Disables timer FL interrupts
1
Enables timer FL interrupts
Bit 1—Timer C Interrupt Enable (IENTC): Bit 1 is used in the H8/3857 Group to enable or
disable timer C overflow or underflow interrupt requests. In the H8/3854 Group, this bit must
always be cleared to 0.
Bit 1: IENTC
Description
0
Disables timer C interrupts
1
Enables timer C interrupts
Bit 0—Timer B Interrupt Enable (IENTB): Bit 0 enables or disables timer B overflow or
underflow interrupt requests.
Bit 0: IENTB
Description
0
Disables timer B interrupts
1
Enables timer B interrupts
SCI3 interrupt control is covered in 10.4.2, in the description of serial control register 3 (SCR3).
Interrupt request register 1 (IRR1)
Bit
IRRTA
Initial value
Read/Write
R/W*
Notes: 1. Only a write of 0 for flag clearing is possible.
2. Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A,
SCI1, or IRQ
to IRQ
4
interrupt is accepted. It is necessary to write 0 to clear each flag.
7
6
5
⎯
2
IRRS1*
0
0
1
⎯
1
1
R/W*
interrupt is requested. The flags are not cleared automatically when an
0
4
3
IRRI4
IRRI3
IRRI2*
0
0
1
1
R/W*
R/W*
R/W*
Rev.3.00 Jul. 19, 2007 page 79 of 532
3. Exception Handling
(initial value)
(initial value)
(initial value)
2
1
0
2
IRRI1
IRRI0
0
0
0
1
1
R/W*
R/W*
REJ09B0397-0300
1
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