Table of Contents
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13.2.1 Index Register (IR) .............................................................................................. 330
13.2.2 Control Register 1 (LR0) ..................................................................................... 331
13.2.3 Control Register 2 (LR1) ..................................................................................... 333
13.2.4 Address Register (LR2) ....................................................................................... 335
13.2.5 Frame Frequency Setting Register (LR3) ............................................................ 336
13.2.6 Display Data Register (LR4)................................................................................ 338
13.2.7 Display Start Line Register (LR5) ....................................................................... 338
13.2.8 Blink Register (LR6)............................................................................................ 339
13.2.9 Blink Start Line Register (LR8)........................................................................... 339
13.2.10 Blink End Line Register (LR9)............................................................................ 340
13.2.11 Contrast Control Register (LRA)......................................................................... 340
13.3 Operation .......................................................................................................................... 342
13.3.1 System Overview................................................................................................. 342
13.3.2 CPU Interface ...................................................................................................... 343
13.3.3 LCD Drive Pin Functions .................................................................................... 346
13.3.4 Display Memory Configuration and Display....................................................... 347
13.3.5 Display Data Output ............................................................................................ 349
13.3.6 Register and Display Memory Access ................................................................. 353
13.3.7 Scroll Function..................................................................................................... 356
13.3.8 Blink Function ..................................................................................................... 358
13.3.9 Module Standby Mode......................................................................................... 360
13.3.10 Power-On and Power-Off Procedures.................................................................. 361
13.3.11 Power Supply Circuit........................................................................................... 362
13.3.12 LCD Drive Power Supply Voltages..................................................................... 363
13.3.13 LCD Voltage Generation Circuit ......................................................................... 365
13.3.14 Contrast Control Circuit....................................................................................... 373
13.3.15 LCD Drive Bias Selection Circuit ....................................................................... 374
14.1 Overview........................................................................................................................... 375
14.1.1 Features................................................................................................................ 375
14.1.2 Block Diagram..................................................................................................... 376
14.1.3 Pin Configuration................................................................................................. 377
14.1.4 Register Configuration......................................................................................... 377
14.2 Register Descriptions ........................................................................................................ 378
14.2.1 Index Register (IR) .............................................................................................. 378
14.2.2 Control Register 1 (LR0) ..................................................................................... 378
14.2.3 Control Register 2 (LR1) ..................................................................................... 379
14.2.4 Address Register (LR2) ....................................................................................... 381
14.2.5 Frame Frequency Setting Register (LR3) ............................................................ 382
Rev.3.00 Jul. 19, 2007 page xxii of xxiv
REJ09B0397-0300
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