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SSR—Serial status register
Bit
TDRE
Initial value
Read/Write
R/(W)
Multiprocessor bit receive
0 Indicates reception of data in which the multiprocessor bit is 0
1 Indicates reception of data in which the multiprocessor bit is 1
Transmit end
0 Indicates that transmission is in progress
[Clearing conditions]
1 Indicates that a transmission has ended
[Setting conditions]
Parity error
0 Indicates that data receiving is in progress or has been completed
[Clearing condition]
1 Indicates that a parity error occurred in data receiving
[Setting condition]
Framing error
0 Indicates that data receiving is in progress or has been completed
[Clearing condition]
1 Indicates that a framing error occurred in data receiving
[Setting condition]
Overrun error
0 Indicates that data receiving is in progress or has been completed
[Clearing condition]
1 Indicates that an overrun error occurred in data receiving
[Setting condition]
Receive data register full
0 Indicates there is no receive data in RDR
[Clearing conditions]
1 Indicates that there is receive data in RDR
[Setting condition]
Transmit data register empty
0 Indicates that transmit data written to TDR has not been transferred to TSR
[Clearing conditions]
1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR
[Setting conditions]
Note: Only a write of 0 for flag clearing is possible.
*
7
6
5
RDRF
OER
1
0
0
*
R/(W)
*
R/(W)
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
When bit TE in serial control register 3 (SCR3) is 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
After reading PER = 1, cleared by writing 0
When the sum of 1s in received data plus the parity bit does not match
the parity mode bit (PM) setting in the serial mode register (SMR)
After reading FER = 1, cleared by writing 0
The stop bit at the end of receive data is checked and found to be 0
After reading OER = 1, cleared by writing 0
When reception of the next serial data is completed while RDRF is set to 1
After reading RDRF = 1, cleared by writing 0.
When data is read from RDR by an instruction.
When receiving ends normally, with receive data transferred from RSR to RDR
After reading TDRE = 1, cleared by writing 0.
When data is written to TDR by an instruction.
When bit TE in serial control register 3 (SCR3) is 0.
When data is transferred from TDR to TSR.
Appendix B Internal I/O Registers
4
3
FER
PER
0
0
*
R/(W)
*
R/(W)
*
Multiprocessor bit transmit
0 The multiprocessor bit in transmit data is 0
1 The multiprocessor bit in transmit data is 1
Rev.3.00 Jul. 19, 2007 page 481 of 532
H'AC
2
1
TEND
MPBR
1
0
R
R
REJ09B0397-0300
SCI3
0
MPBT
0
R/W
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