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14.3.7
Module Standby Mode
The LCD controller has a module standby function that enables low power consumption to be
achieved. In module standby mode, the current supply to the built-in bleeder resistances is halted,
and segment and common outputs go to the V
internal register data is retained, except for the DISP, LPS1, and LPS0 bits in control register 2
(LR1). The control registers can still be accessed in the module standby state. Figure 14.9 shows
the procedures for initiating and clearing module standby mode. The initiation and clearing
procedures must be followed exactly in order to protect the display memory contents.
When the CPU is placed in standby mode, set the LSBY bit in control register 1 (LR0) to 1 before
executing the standby instruction. After clearing standby mode, follow the module standby
clearing procedure to start display.
Initiation
Clearing
Note: * Do not set to 1 when an external power supply is used.
Figure 14.9 Module Standby Mode and Standby Mode Initiation and Clearing Procedures
(display-off state) level. Display RAM and
SS
Set LSBY to 1
Module standby mode initiated
Clear LSBY to 0
Set LPS1*, LPS0*, and DISP to 1
14. Dot Matrix LCD Controller (H8/3854 Group)
Internal operation halts
Internal operation starts
Display starts
Rev.3.00 Jul. 19, 2007 page 395 of 532
REJ09B0397-0300
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