Renesas F-ZTAT H8 Series Hardware Manual page 106

3. Exception Handling
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7: IRRTA Description
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1 Setting condition:
When the timer A counter value overflows (goes from H'FF to H'00)
Bit 6—SCI1 Interrupt Request Flag (IRRS1): Bit 6 is used in the H8/3857 Group. In the
H8/3854 Group, this bit must always be cleared to 0.
Bit 6: IRRS1 Description
0 Clearing condition:
When IRRS1 = 1, it is cleared by writing 0
1 Setting condition:
When an SCI1 transfer is completed
Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified.
Bits 4, 3, 1, and 0—IRQ
IRRI1, IRRI0)
Bit n: IRRIn Description
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0 to IRRIn
1 Setting condition:
IRRIn is set when pin IRQ
edge is detected
Note: n = 4, 3, 1, or 0
Bit 2—IRQ Interrupt Request Flag (IRRI2): Bit 2 is used in the H8/3857 Group. In the
2
H8/3854 Group, this bit must always be cleared to 0.
Bit 2: IRRI2 Description
0 Clearing condition:
When IRRI2 = 1, it is cleared by write 0 to IRRI2
1 Setting condition:
IRRI2 is set when pin IRQ
edge is detected
Rev.3.00 Jul. 19, 2007 page 80 of 532
REJ09B0397-0300
, IRQ , IRQ , and IRQ
4 3 1
n
2
Interrupt Request Flags (IRRI4, IRRI3,
0
is set to interrupt input, and the designated signal
is set to interrupt input, and the designated signal
(initial value)
(initial value)
(initial value)
(initial value)