Renesas F-ZTAT H8 Series Hardware Manual page 289

The receive shift register (RSR) is for receiving serial data.
Serial data is input in LSB (bit 0) order into RSR from pin RXD, converting it to parallel data.
After each byte of data has been received, the byte is automatically transferred to the receive data
register (RDR).
RSR cannot be read or written directly by the CPU.
Receive Data Register (RDR)
Bit
RDR7
Initial value
Read/Write
The receive data register (RDR) is an 8-bit register for storing received serial data.
Each time a byte of data is received, the received data is transferred from the receive shift register
(RSR) to RDR, completing a receive operation. Thereafter RSR again becomes ready to receive
new data. RSR and RDR form a double buffer mechanism that allows data to be received
continuously.
RDR is exclusively for receiving data and cannot be written by the CPU.
RDR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Transmit Shift Register (TSR)
Bit
Read/Write
The transmit shift register (TSR) is for transmitting serial data.
Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted
from pin TXD, starting from the LSB (bit 0).
After one byte of data has been sent, the next byte is automatically transferred from TDR to TSR,
and the next transmission begins. If no data has been written to TDR (1 is set in TDRE), there is
no data transfer from TDR to TSR.
7 6 5
RDR6 RDR5
0 0 0
R R R
7 6 5
⎯ ⎯ ⎯
10. Serial Communication Interface
4 3
RDR4 RDR3 RDR2
0 0
R R
4 3
⎯ ⎯
Rev.3.00 Jul. 19, 2007 page 263 of 532
2 1
RDR1 RDR0
0 0
R R R
2 1
⎯ ⎯ ⎯
REJ09B0397-0300
0
0
0