Renesas F-ZTAT H8 Series Hardware Manual page 508

Appendix B Internal I/O Registers
RDR—Receive data register
Bit
RDR7
Initial value
Read/Write R
TMA—Timer mode register A
Bit
TMA7
Initial value
Read/Write R/W
Clock output select
φ/32
0 0 0
φ/16
1
φ/8
1 0
φ/4
1
φ /32
1 0 0
W
φ /16
1
W
φ /8
1 0
W
φ /4
1
W
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REJ09B0397-0300
7 6 5
RDR6 RDR5
0 0 0
R R
7 6 5
TMA6 TMA5
0 0 0
R/W R/W
Internal clock select
TMA3 TMA2 TMA1
0 0
1
1 0
1
4 3
RDR4 RDR3
0 0
R R
4 3
— TMA3
1 0
— R/W
Prescaler and Divider Ratio
TMA0 or Overflow Period
0 0 PSS
1 PSS
1 0 PSS
1 PSS
0 0 PSS
1 PSS
1 0 PSS
1 PSS
0 0 PSW
1 PSW
1 0 PSW
1 PSW
0 0 PSW and TCA are reset
1
1 0
1
H'AD
2 1
RDR2 RDR1
0 0
R R
H'B0
2 1
TMA2 TMA1
0 0
R/W R/W
φ/8192
φ/4096
φ/2048
φ/512
φ/256
φ/128
φ/32
φ/8
1 s
0.5 s
0.25 s
0.03125 s
SCI3
0
RDR0
0
R
Timer A
0
TMA0
0
R/W
Function
Interval
timer
Time
base