Renesas F-ZTAT H8 Series Hardware Manual page 315

SCI3 operates as follows during data transmission.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10.14. Next, TDRE is checked as the stop bit is being transmitted.
If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of
the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent
the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3
is set to 1.
Figure 10.11 shows a typical operation in asynchronous transmission mode.
Start
bit
Serial
1 0
data
TDRE
TEND
LSI
TXI request
operation
User
processing
Figure 10.11 Typical Transmit Operation in Asynchronous Mode
Receiving: Figure 10.12 shows a typical flow chart for receiving serial data. After SCI3
initialization, follow the procedure below.
Transmit Parity
data bit
D0 D1 D7 0/1
1 frame
TDRE cleared to 0 TXI request
Write data in TDR
(8-Bit Data, Parity Bit Added, and 1 Stop Bit)
10. Serial Communication Interface
Stop Start Transmit
bit bit data
1 0 D0 D1
Rev.3.00 Jul. 19, 2007 page 289 of 532
Parity Stop
bit bit
D7 0/1 1
1 frame
TEI request
REJ09B0397-0300
Mark
state
1