Renesas F-ZTAT H8 Series Hardware Manual page 91

Example 2: When a BSET instruction is executed on port 3
P3 and P3 are designated as input pins, with a low-level signal input at P3
7 6
signal at P3 . The remaining pins, P3
6
example, the BSET instruction is used to change pin P3
[A: Prior to executing BSET]
P3
7
Input/output Input
Pin state Low
level
PCR3 0
PDR3 1
[B: BSET instruction executed]
BSET #0 ,
[C: After executing BSET]
P3
7
Input/output Input
Pin state Low
level
PCR3 0
PDR3 0
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3 and P3 are input pins, the CPU reads the pin states (low-level and high-level input). P3
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to P3 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of
0
H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
to P3 , are output pins and output low-level signals. In this
5 0
P3 P3
6 5
Input Output
High Low
level level
0 1
0 0
@PDR3 The BSET instruction is executed designating port 3.
P3 P3
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Input Output
High Low
level level
0 1
1 0
to high-level output.
0
P3 P3 P3
4 3
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
P3 P3 P3
4 3
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
Rev.3.00 Jul. 19, 2007 page 65 of 532
2. CPU
and a high-level
7
P3 P3
2 1 0
Output Output
Low Low
level level
1 1
0 0
P3 P3
2 1 0
Output Output
Low High
level level
1 1
0 1
REJ09B0397-0300
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