Table of Contents
Advertisement
Table A.3
Number of Cycles in Each Instruction
Execution Status
(Instruction Cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note:
*
Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data
Access for details.
On-Chip Memory
S
2
I
S
J
S
K
S
L
S
M
S
1
N
Appendix A CPU Instruction Set
Access Location
On-Chip Peripheral Module
⎯
2 or 3*
⎯
Rev.3.00 Jul. 19, 2007 page 453 of 532
REJ09B0397-0300
Advertisement
Table of Contents
