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Example: Direct transfer time for the H8/3857 Group and H8/3854 Group
= (2 + 1) × 16tosc + 14 × 2tosc = 76 tosc
Legend:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
Time Required before Direct Transfer from Subactive Mode to Active (High-Speed) Mode:
A direct transfer is made from subactive mode to active (high-speed) mode when a SLEEP
instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit
in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is
set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP
instruction execution to interrupt exception handling completion is calculated by expression (3)
below.
Direct transfer time = (number of states for SLEEP instruction execution + number of
Example: Direct transfer time for the H8/3857 Group and H8/3854 Group
(when CPU clock frequency is φw/8 and wait time is 8192 states)
= (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc
Legend:
tosc:
tw:
tcyc:
tsubcyc: Subclock (φ
Time Required before Direct Transfer from Subactive Mode to Active (Medium-Speed)
Mode: A direct transfer is made from subactive mode to active (medium-speed) mode when a
SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the
LSON bit in SYSCR1 is cleared to 0, the MSON and DTON bits in SYSCR2 are set to 1, and the
TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction
execution to interrupt exception handling completion is calculated by expression (4) below.
Direct transfer time = (number of states for SLEEP instruction execution + number of
states for internal processing) × tsubcyc before transition + (wait
time designated by STS2 to STS0 bits in SCR + number of states
for interrupt exception handling execution) × tcyc after transition
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
) cycle time
SUB
states for internal processing) × tsubcyc before transition + (wait
time designated by STS2 to STS0 bits in SCR + number of states
for interrupt exception handling execution) × tcyc after transition
5. Power-Down Modes
Rev.3.00 Jul. 19, 2007 page 117 of 532
...... (3)
...... (4)
REJ09B0397-0300
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