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IENR1—Interrupt enable register 1
Bit
IENTA
Initial value
Read/Write
R/W
SCI1 interrupt enable
0 Disables SCI1 interrupts
1 Enables SCI1 interrupts
Timer A interrupt enable
0 Disables timer A interrupts
1 Enables timer A interrupts
Note: * IENS1 and IEN2 are functions of the H8/3857 Group only.
In the H8/3854 Group these bits are reserved, and must always be cleared to 0.
7
6
5
IENS1 *
IENWP
0
0
0
R/W
R/W
Wakeup interrupt enable
0 Disables interrupt requests from WKP to WKP
Enables interrupt requests from WKP to WKP
1
Appendix B Internal I/O Registers
H'F3
4
3
IEN4
IEN3
0
0
R/W
R/W
IRQ to IRQ interrupt enable
4
0
0 Disables interrupt request IRQ
Enables interrupt request IRQ
1
Note: n = 4 to 0
7
7
Rev.3.00 Jul. 19, 2007 page 503 of 532
System control
2
1
IEN2 *
IEN1
IEN0
0
0
R/W
R/W
R/W
n
n
0
0
REJ09B0397-0300
0
0
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