Display Data Register (Lr4) - Renesas F-ZTAT H8 Series Hardware Manual

Table 14.3 Register Settings, Division Ratios, and Frame Frequencies at Each Display Duty
FS2 FS1
0 0
1
1 0
1
14.2.6

Display Data Register (LR4)

Bit
7
D7
Initial value
Undefined
Read/Write
R/W
LR4 is an 8-bit read/write register used to perform read/write access to the display memory
specified by XA2 to XA0 and YA3 to YA0 in LR2.
In a write to display memory, the write is performed directly to the display memory via this
register. In a read, the data is temporarily latched into this register before being output to the bus.
After a reset, the display memory and LR4 contents are undefined.
Division
FS0 ratio r
0 2
1 4
0 8
1 16
0 32
1 64
0 128
1 Setting
prohibited
6 5
D6 D5
Undefined Undefined
R/W R/W
14. Dot Matrix LCD Controller (H8/3854 Group)
Display Duty 1/N
1/8
Subclock Frequency f
32.768 38.4
Frame Frequency f
2048.0 2400.0
1024.0 1200.0
512.0 600.0
256.0 300.0
128.0 150.0
64.0 75.0
32.0 37.5
Setting Setting
prohibited prohibited
4 3
D4 D3
Undefined Undefined
R/W R/W
Rev.3.00 Jul. 19, 2007 page 383 of 532
1/16
(kHz)
W
32.768
(Hz)
F
1024.0
512.0
256.0
128.0
64.0
32.0
16.0
Setting
prohibited
2 1
D2 D1
Undefined Undefined
R/W R/W
REJ09B0397-0300
38.4
1200.0
600.0
300.0
150.0
75.0
37.5
18.8
Setting
prohibited
0
D0
Undefined
R/W