Renesas F-ZTAT H8 Series Hardware Manual page 469

Table A.1 Instruction Set
Mnemonic
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
POP Rd
Operation
B #xx:8 → Rd8
B Rs8 → Rd8
B @Rs16 → Rd8
B @(d:16, Rs16)→ Rd8
B @Rs16 → Rd8
Rs16+1 → Rs16
B @aa:8 → Rd8
B @aa:16 → Rd8
B Rs8 → @Rd16
B Rs8 → @(d:16, Rd16)
B Rd16–1 → Rd16
Rs8 → @Rd16
B Rs8 → @aa:8
B Rs8 → @aa:16
W #xx:16 → Rd
W Rs16 → Rd16
W @Rs16 → Rd16
W @Rs16 → Rd16
Rs16+2 → Rs16
W @aa:16 → Rd16
W Rs16 → @Rd16
W Rd16–2 → Rd16
Rs16 → @Rd16
W Rs16 → @aa:16
W @SP → Rd16
SP+2 → SP
Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (Bytes)
2
2
2
4
2
2
4
2
4
2
2
4
4
2
2
4
2
4
2
4
2
4
2
Rev.3.00 Jul. 19, 2007 page 443 of 532
Condition Code
I H N Z V C
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 2
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 4
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
⎯ ⎯ 0 ⎯ 6
REJ09B0397-0300