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Appendix B Internal I/O Registers
B.2
Register Descriptions
Register
acronym
TMC—Timer mode register C
Bit
numbers
Bit
Initial bit
values
Initial value
Read/Write
Possible types of access
R
Read only
W
Write only
R/W
Read and write
Rev.3.00 Jul. 19, 2007 page 468 of 532
REJ09B0397-0300
Register
name
H'B4
7
6
5
TMC7
TMC6
TMC5
0
0
0
R/W
R/W
R/W
Clock select
0
0 0
1 0
1 0 0
1 0
Counter up/down control
0 0
TCC is an up-counter
1
TCC is a down-counter
1 *
TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
Legend: * Don't care
Auto-reload function select
0
Interval function selected
1
Auto-reload function selected
Address to which the
register is mapped
4
3
2
⎯
⎯
TMC2
1
1
0
⎯
⎯
R/W
φ/8192
Internal clock:
φ/2048
1
Internal clock:
φ/512
Internal clock:
φ/64
1
Internal clock:
φ/16
Internal clock:
φ/4
1
Internal clock:
φ /4
Internal clock:
W
1
External event (TMIC):
Rising or falling edge
Name of
on-chip
supporting
module
Timer C
1
0
TMC1
TMC0
0
0
Names of the
bits. Dashes
R/W
R/W
(⎯) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
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