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9. Timers
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 select the clock to be input to
TCW.
Bit 2:
Bit 1:
CKS2
CKS1
0
0
1
1
0
1
9.6.3
Operation
The watchdog timer is provided with an 8-bit counter that increments with each input clock pulse.
If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set to 1, TCW
begins counting up. When a clock pulse is input after the TCW count value has reached H'FF, the
watchdog timer overflows and an internal reset signal is generated one base clock (φ) cycle later.
The internal reset signal is output for a period of 512 φ
and when a value is set in TCW, the count-up starts from that value. An overflow period in the
range of 1 to 256 input clock cycles can therefore be set, according to the TCW value.
Figure 9.9 shows an example of watchdog timer operation.
Rev.3.00 Jul. 19, 2007 page 246 of 532
REJ09B0397-0300
Bit 0:
CKS0
Description
Internal clock: φ/64
0
Internal clock: φ/128
1
Internal clock: φ/256
0
Internal clock: φ/512
1
Internal clock: φ/1024
0
Internal clock: φ/2048
1
Internal clock: φ/4096
0
Internal clock: φ/8192
1
clock cycles. TCW is a writable counter,
osc
(initial value)
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