Renesas F-ZTAT H8 Series Hardware Manual page 161

Automatic SCI Bit Rate Adjustment
Start
bit
Figure 6.9 RXD Input Signal in Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the chip measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host . The SCI transmit/receive
format should be set as 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the
transmission from the host from the measured low period, and transmits one H'00 byte to the host
to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host's transmission bit rate and the chip's system clock frequency, there will be a
discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the
host's transfer bit rate should be set to 2400, 4800, or 9600 bps*
Table 6.6 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the chip's bit rate is possible. The boot program should be executed within this
system clock oscillation frequency range*
Notes: 1. Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
used.
2. Although the chip may also perform automatic bit rate adjustment with bit rate and
system clock combinations other than those shown in table 6.6, a degree of error will
arise between the bit rates of the host and the chip, and subsequent transfer will not be
performed normally. Therefore, only a combination of bit rate and system clock
oscillation frequency within one of the ranges shown in table 6.6 can be used for boot
mode execution.
D0 D1 D2
Low period (9 bits) measured (H'00 data)
2
.
D3 D4 D5
1
.
Rev.3.00 Jul. 19, 2007 page 135 of 532
6. ROM
Stop
D6 D7
bit
High period
(1 or more bits)
REJ09B0397-0300