Watchdog Timer [H8/3857F And H8/3854F Only]; Overview - Renesas F-ZTAT H8 Series Hardware Manual

• 8-bit timer mode
⎯ TCFH and OCRFH
The output at pin TMOFH toggles when there is a compare match. If the compare match
signal occurs at the same time as new data is written in TCRF by a MOV instruction,
however, the new value written in bit TOLH will be output at pin TMOFH.
If an OCRFH write occurs at the same time as a compare match signal, the compare match
signal is inhibited. If a compare match occurs between the written data and the counter
value, however, a compare match signal will be generated at that point. The compare match
signal is output in synchronization with the TCFH clock.
If a TCFH write occurs at the same time as an overflow signal, the overflow signal is not
output.
⎯ TCFL and OCRFL
The output at pin TMOFL toggles when there is a compare match. If the compare match
signal occurs at the same time as new data is written in TCRF by a MOV instruction,
however, the new value written in bit TOLL will be output at pin TMOFL.
If an OCRFL write occurs at the same time as a compare match signal, the compare match
signal is inhibited. If a compare match occurs between the written data and the counter
value, however, a compare match signal will be generated at that point. The compare match
signal is output in synchronization with the TCFL clock, so if this clock is stopped no
compare match signal will be generated, even if a compare match occurs.
If a TCFL write occurs at the same time as an overflow signal, the overflow signal is not
output.
9.6

Watchdog Timer [H8/3857F and H8/3854F Only]

9.6.1

Overview

The watchdog timer (WDT) is equipped with an 8-bit counter that is incremented by an input
clock. An internal chip reset can be executed if the counter overflows because it is not updated
normally due to a system crash, etc.
This watchdog timer is used by the flash memory programming control program.
Features
Features of the watchdog timer are given below.
• Choice of eight internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096,
φ/8192)
• Reset signal generated on counter overflow
Rev.3.00 Jul. 19, 2007 page 241 of 532
9. Timers
REJ09B0397-0300