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Notes on Use of Boot Mode
1. When the chip comes out of reset in boot mode, it measures the low period of the input at the
SCI3's RXD pin. The reset should end with RXD high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the RXD input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD and TXD lines should be pulled up on the board.
5. Before branching to the programming control program (RAM area address H'FB80), the chip
terminates transmit and receive operations by the on-chip SCI3 (by clearing the RE and TE
bits to 0 in SCR3), but the adjusted bit rate value remains set in BRR. The transmit data output
pin, TXD, goes to the high-level output state (PCR4
port data register 4).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by making the pin settings shown in table 6.5, and then executing a
reset start.
Boot mode can be exited by waiting at least 10 system clock cycles after driving the reset pin
2
low*
, then setting the FWE, TEST2, and TEST pins to execute reset release*
also be exited when a WDT overflow reset occurs.
Do not change the input levels at the FWE, TEST2, and TEST pins while in boot mode. The
FWE pin must not be driven low while the boot program is running or flash memory is being
programmed or erased*
7. If the input level of the TEST2, TEST, or FWE pin is changed (for example, from low to high)
during a reset, the MCU's operating mode will change, and as a result, the port states will also
change. Therefore, care must be taken to make pin settings to prevent these pins from
becoming output signal pins during a reset, or to prevent collision with signals outside the
MCU.
Notes: 1. TEST2, TEST, and FWE pin input must satisfy the mode programming setup time (t
= 4 states) with respect to the reset release timing.
2. See section 3.2.2, Reset Sequence, and section 6.9, Flash Memory Programming and
Erasing Precautions.
3
.
= 1 in port control register 4, P4
2
Rev.3.00 Jul. 19, 2007 page 137 of 532
6. ROM
= 1 in
2
1
. Boot mode can
MDS
REJ09B0397-0300
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